Datasheet

Standard Timer (TIM)
M68HC12B Family Data Sheet, Rev. 9.1
154 Freescale Semiconductor
12.3.13 Timer Test Register
Read: Anytime
Write: Only in special mode (SMODN = 0)
TCBYP — Timer Divider Chain Bypass Bit
0 = Normal operation
1 = 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is bypassed.
The clock drives both halves directly.
PCBYP — Pulse Accumulator Divider Chain Bypass Bit
0 = Normal operation
1 = 16-bit pulse accumulator counter is divided into two 8-bit halves and the prescaler is bypassed.
The clock drives both halves directly.
12.3.14 Timer Port Data Register
Read: Anytime; inputs return pin level; outputs return pin driver input level
Write: Data stored in an internal latch; drives pins only if configured for output
NOTE
Writes do not change pin state when the pin is configured for timer output.
The minimum pulse width for pulse accumulator input should always be
greater than two module clocks due to input synchronizer circuitry. The
minimum pulse width for the input capture should always be greater than
the width of two module clocks due to input synchronizer circuitry.
Address: $00AD
Bit 7654321Bit 0
Read:000000TCBYPPCBYP
Write:
Reset:00000000
= Unimplemented
Figure 12-27. Timer Test Register (TIMTST)
Address: $00AE
Bit 7654321Bit 0
Read:
PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0
Write:
Reset:00000000
Timer: I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0
PA: PAI
Figure 12-28. Timer Port Data Register (PORTT)