Datasheet

Timer Operation in Modes
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 155
12.3.15 Data Direction Register for Timer Port
Read: Anytime
Write: Anytime
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases the data direction bits will not be changed, but they have no affect on the
direction of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated
timer output compare is disabled. Input captures do not override the DDRT settings.
12.4 Timer Operation in Modes
Stop — Timer is off since both PCLK and ECLK are stopped.
BDM— Timer keeps running, unless TSBCK = 1.
Wait — Counters keep running, unless TSWAI = 1.
Normal — Timer keeps running, unless TEN = 0.
TEN = 0 —All timer operations are stopped, registers may be accessed.
Gated pulse accumulator ÷64 clock is also disabled.
PAEN = 0 —All pulse accumulator operations are stopped.
Registers may be accessed.
Address: $00AF
Bit 7654321Bit 0
Read:
DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0
Write:
Reset:00000000
Figure 12-29. Data Direction Register for Timer Port (DDRT)