Datasheet

Enhanced Capture Timer Modes of Operation
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 161
Figure 13-1. Timer Block Diagram in Latch Mode
16 BIT MAIN TIMER
PT1
COMPARATOR
TC0H HOLD
PT0
PT3
PT2
PT4
PT5
PT6
PT7
EDG0
EDG1
EDG2
EDG3
MUX
PRESCALER
M CLOCK
16-BIT LOAD REGISTER
16-BIT MODULUS
0
RESET
EDG0
EDG1
EDG2
EDG4
EDG5
EDG3
EDG6
EDG7
÷ 1, 2, ..., 128
÷ 1, 4, 8, 16
16-BIT FREE-RUNNING
LATCH
UNDERFLOW
MAIN TIMER
PRESCALER
TC0 CAPTURE/COMPARE
PIN
DELAY
P CLOCK
TC1H HOLD
TC2H HOLD
TC3H HOLD
MUX
MUX
MUX
PA0H HOLD
PAC0
0
RESET
PA1H HOLD
PAC1
0
RESET
PA2H HOLD
PAC2
0
RESET
PA3H HOLD
PAC3
WRITE $0000
TO MODULUS
ICLAT, LATQ, BUFEN
(FORCE LATCH)
LATQ
(MDC LATCH
DOWN COUNTER
LOGIC
PIN
LOGIC
PIN
LOGIC
PIN
LOGIC
PIN
LOGIC
PIN
LOGIC
PIN
LOGIC
PIN
LOGIC
COUNTER
DELAY
COUNTER
DELAY
COUNTER
DELAY
COUNTER
REGISTER
COMPARATOR
TC1 CAPTURE/COMPARE
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
COMPARATOR
TC2 CAPTURE/COMPARE
REGISTER
COMPARATOR
TC3 CAPTURE/COMPARE
REGISTER
COMPARATOR
TC4 CAPTURE/COMPARE
REGISTER
COMPARATOR
TC5 CAPTURE/COMPARE
REGISTER
COMPARATOR
TC6 CAPTURE/COMPARE
REGISTER
COMPARATOR
TC7 CAPTURE/COMPARE
REGISTER
COUNTER
ENABLE)