Datasheet

Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
164 Freescale Semiconductor
Figure 13-3. 8-Bit Pulse Accumulators Block Diagram
HOST CPU DATA BUS
PT0
LOAD HOLDING REGISTER AND RESET PULSE ACCUMULATOR
0
0
EDG3
EDG2
EDG1
EDG0
EDGE DETECTOR DELAY COUNTER
INTERRUPT
INTERRUPT
PT1
EDGE DETECTOR DELAY COUNTER
PT2
EDGE DETECTOR DELAY COUNTER
PT3
EDGE DETECTOR DELAY COUNTER
8-BIT PAC0 (PACN0)
PA0H HOLDING
0
8-BIT PAC1 (PACN1)
PA1H HOLDING
0
8-BIT PAC2 (PACN2)
PA2H HOLDING
0
8-BIT PAC3 (PACN3)
PA3H HOLDING
REGISTER
REGISTER
REGISTER
REGISTER