Datasheet

Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
166 Freescale Semiconductor
13.4.1 Timer Input Capture/Output Compare Select Register
Read: Anytime
Write: Anytime
IOS[7:0] — Input Capture or Output Compare Channel Configuration Bits
0 = The corresponding channel acts as an input capture.
1 = The corresponding channel acts as an output compare.
13.4.2 Timer Compare Force Register
Read: Anytime but, will always return $00 (1 state is transient).
Write: Anytime
FOC[7:0] — Force Output Compare Action Bits for Channel 7–0
A write to this register with the corresponding data bit(s) set causes the action which is programmed
for output compare “n” to occur immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the interrupt flag does not get set.
13.4.3 Output Compare 7 Mask Register
Read: Anytime
Write: Anytime
Address: $0080
Bit 7654321Bit 0
Read:
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
Reset:00000000
Figure 13-5. Timer Input Capture/Output Compare
Select Register (TIOS)
Address: $0081
Bit 7654321Bit 0
Read:
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Write:
Reset:00000000
Figure 13-6. Timer Compare Force Register (CFORC)
Address: $0082
Bit 7654321Bit 0
Read:
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Write:
Reset:00000000
Figure 13-7. Output Compare 7 Mask Register (OC7M)