Datasheet

Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
168 Freescale Semiconductor
13.4.5 Timer Count Registers
Read: Anytime
Write: Has no meaning or effect in the normal mode; only writable in special
modes (SMODN = 0)
The 16-bit main timer is an up-counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
13.4.6 Timer System Control Register
Read: Anytime
Write: Anytime
TEN — Timer Enable Bit
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the E ÷
64 is generated by the timer prescaler.
0 = Disables the main timer, including the counter; can be used for reducing power consumption
1 = Allows the timer to function normally
Address: $0084
Bit 7654321Bit 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Address: $0085
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
= Unimplemented
Figure 13-10. Timer Count Registers (TCNT)
Address: $0086
Bit 7654321Bit 0
Read:
TEN TSWAI TSBCK TFFCA
Write:
Reset:00000000
= Unimplemented
Figure 13-11. Timer System Control Register (TSCR)