Datasheet

Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
170 Freescale Semiconductor
To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture
or output compare 7 and 0, respectively, the user must set the corresponding bits IOSn = 1, OMn = 0,
and OLn = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
Read: Anytime
Write: Anytime
EDGnB and EDGnA — Input Capture Edge Control Bits
These eight pairs of control bits configure the input capture edge detector circuits. See Table 13-2.
Table 13-1. Compare Result Output Action
OMn OLn Action
0 0 Timer disconnected from output pin logic
0 1 Toggle OCn output line
1 0 Clear OCn output line to 0
1 1 Set OCn output line to 1
Address: $008A
Bit 7654321Bit 0
Read:
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write:
Reset:00000000
Figure 13-14. Timer Control Register 3 (TCTL3)
Address: $008B
Bit 7654321Bit 0
Read:
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Write:
Reset:00000000
Figure 13-15. Timer Control Register 4 (TCTL4)
Table 13-2. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)