Datasheet

Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
172 Freescale Semiconductor
PR2, PR1, and PR0 — Timer Prescaler Select Bits
These three bits specify the number of ÷2 stages that are to be inserted between the module clock and
the main timer counter. See Table 13-3. The newly selected prescale factor will not take effect until the
next synchronized edge where all prescale counter stages equal 0.
13.4.9 Main Timer Interrupt Flag Registers
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be
cleared). Writing a 0 will not affect current bit status.
C7F–C0F — Input Capture/Output Compare Channel n Flag
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a 1
to the bit.
Use of the TFMOD bit in the input control system control register (ICSYS) register ($AB) in conjunction
with the use of the ICOVW register ($AA) allows a timer interrupt to be generated after capturing two
values in the capture and holding registers instead of generating an interrupt for every capture.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel ($90–$9F) will cause the corresponding channel flag CnF to be cleared. See Figure 13-19.
Table 13-3. Prescaler Selection
Value PR2 PR1 PR0 Prescale Factor
0000 1
1001 2
2010 4
3011 8
4100 16
5101 32
6110 64
7111 128
Address: $008E
Bit 7654321Bit 0
Read:
C7F C6F C5F C4F C3F C2F C1F C0F
Write:
Reset:00000000
Figure 13-18. Main Timer Interrupt Flag 1 (TFLG1)