Datasheet

Timer Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 173
Figure 13-19. C3F–C0F Interrupt Flag Setting
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be
cleared). Any access to TCNT will clear the TFLG2 register, if the TFFCA
bit in the TSCR register is set.
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit to 1.
TOF — Timer Overflow Flag
TOF is set when the 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. See the explanation of the TCRE control
bit in 13.4.8 Timer Interrupt Mask Registers.)
13.4.10 Timer Input Capture/Output Compare Registers
Address: $008F
Bit 7654321Bit 0
Read:
TOF0000000
Write:
Reset:00000000
Figure 13-20. Main Timer Interrupt Flag 2 (TFLG2)
Address: $0090–$0091
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Figure 13-21. Timer Input Capture/Output Compare Register 0 (TC0)
PTN
EDGE
DELAY
16-BIT MAIN TIMER
TCNH IC HOLDING
BUFEN • LATQ • TFMOD
SET CNF
DETECTOR
COUNTER
REGISTER
TCN INPUT CAPTURE
REGISTER
INTERRUPT