Datasheet

Enhanced Capture Timer (ECT) Module
M68HC12B Family Data Sheet, Rev. 9.1
184 Freescale Semiconductor
TCBYP — Main Timer Divider Chain Bypass Bit
0 = Normal operation
1 = For testing only. The 16-bit free-running timer counter is divided into two 8-bit halves and the
prescaler is bypassed. The clock drives both halves directly. When the high byte of timer
counter TCNT ($84) overflows from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.
13.4.21 Timer Port Data Register
Read: Anytime (input return pin level; outputs return data register contents)
Write: Data stored in an internal latch (drives pins only if configured for output)
Since the output compare 7 register (OC7) shares pins with the pulse accumulator input, the only way for
the pulse accumulator to receive an independent input from OC7 is by setting both OM7 and OL7 to be
0, and also OC7M7 in OC7M register to be 0. OC7 can still reset the counter if enabled while PT7 is used
as an input to the pulse accumulator.
PORTT can be read anytime. When configured as an input, a read will return the pin level. When
configured as an output, a read will return the latched output data.
NOTE
Writes do not change pin state when the pin is configured for timer output.
The minimum pulse width for pulse accumulator input should always be
greater than the width of two module clocks due to input synchronizer
circuitry. The minimum pulse width for the input capture should always be
greater than the width of two module clocks due to input synchronizer
circuitry.
13.4.22 Data Direction Register for Timer Port
Read: Anytime
Write: Anytime
Address: $00AE
Bit 7654321Bit 0
Read:
PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0
Write:
Timer: I/0C7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0
Reset:00000000
Figure 13-42. Timer Port Data Register (PORTT)
Address: $00AF
Bit 7654321Bit 0
Read:
DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0
Write:
Reset:00000000
Figure 13-43. Data Direction Register for Timer Port (DDRT)