Datasheet

Timer Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 185
DDT[7:0] — Data Direction Bits for Timer Port
The timer forces the I/O state to be an output for each timer port line associated with an enabled output
compare. In these cases the data direction bits will not be changed, but have no effect on the direction
of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. Input captures do not override the DDRT settings.
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
13.4.23 16-Bit Pulse Accumulator B Control Register
Read: Anytime
Write: Anytime
Sixteen-bit pulse accumulator B (PACB) is formed by cascading the 8-bit pulse accumulators PAC1 and
PAC0. When PBEN is set, the PACB is enabled. The PACB shares the input pin with IC0.
PBEN — Pulse Accumulator B System Enable Bit
PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless
pulse accumulator is disabled.
0 = 16-bit pulse accumulator system disabled. Eight-bit PAC1 and PAC0 can be enabled when their
related enable bits in ICPACR ($A8) are set.
1 = Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are
cascaded to form the PACB 16-bit pulse accumulator. When PACB is enabled, the PACN1 and
PACN0 register contents are, respectively, the high and low byte of the PACB. PA1EN and
PA0EN control bits in ICPACR ($A8) have no effect.
PBOVI — Pulse Accumulator B Overflow Interrupt Enable Bit
0 = Interrupt inhibited
1 = Interrupt requested if PBOVF is set
13.4.24 Pulse Accumulator B Flag Register
• Read:Anytime
• Write:Anytime
Address: $00B0
Bit 7654321Bit 0
Read:
0PBEN0000PBOV0
Write:
Reset:00000000
Figure 13-44. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Address: $00B1
Bit 7654321Bit 0
Read:
000000PBOVF0
Write:
Reset:00000000
Figure 13-45. Pulse Accumulator B Flag Register (PBFLG)