Datasheet

Timer Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 187
13.4.26 Modulus Down-Counter Count Registers
Read: Anytime
Write: Anytime
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give different results than accessing them as a word. If the RDMCL bit in MCCTL
register is cleared, reads of the MCCNT register will return the present value of the count register. If the
RDMCL bit is set, reads of the MCCNT will return the contents of the load register.
If a $0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS ($AB) register
are set, the input capture and pulse accumulator registers will be latched. With a $0000 write to the
MCCNT, the modulus counter will stay at 0 and does not set the MCZF flag in MCFLG register.
If modulus mode is enabled (MODMC = 1), a write to this address will update the load register with the
value written to it. The count register will not be updated with the new value until the next counter
underflow. The FLMC bit in MCCTL ($A6) can be used to immediately update the count register with the
new value if an immediate load is desired.
If modulus mode is not enabled (MODMC = 0), a write to this address will clear the prescaler and will
immediately update the counter register with the value written to it and down-counts once to $0000.
13.4.27 Timer Input Capture Holding Registers
Address: $00B6
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Address: $00B7
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:11111111
Figure 13-50. Modulus Down-Counter Count Registers (MCCNT)
Address: $00B8
Bit 7654321Bit 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Address: $00B9
Bit 7654321Bit 0
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
Figure 13-51. Timer Input Capture Holding Register 0 (TC0H)