Datasheet

Byte Data Link Communications (BDLC)
M68HC12B Family Data Sheet, Rev. 9.1
224 Freescale Semiconductor
Figure 15-6. J1850 VPW Received Passive Symbol Times
15.7.4.1 Invalid Passive Bit
See Figure 15-6(1). If the passive-to-active received transition beginning the next data bit or symbol
occurs between the active-to-passive transition beginning the current data bit (or symbol) and A, the
current bit would be invalid.
15.7.4.2 Valid Passive Logic 0
See Figure 15-6(2). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between A and B, the current bit would be considered a logic 0.
15.7.4.3 Valid Passive Logic 1
See Figure 15-6(3). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between B and C, the current bit would be considered a logic 1.
15.7.4.4 Valid EOD Symbol
See Figure 15-6(4). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between C and D, the current symbol would be considered a valid end-of-data symbol (EOD).
A
BC
BA
(1) INVALID PASSIVE BIT
(2) VALID PASSIVE LOGIC 0
(3) VALID PASSIVE LOGIC 1
64 µs
128 µs
CD
(4) VALID EOD SYMBOL
200 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE