Datasheet

Byte Data Link Communications (BDLC)
M68HC12B Family Data Sheet, Rev. 9.1
228 Freescale Semiconductor
the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two extra
logic 1s do not corrupt the current message. However, if the BDLC has lost arbitration due to noise on the
bus, then the two extra logic 1s ensure that the current message is detected and ignored as a
noise-corrupted message.
Figure 15-10. J1850 VPW Bitwise Arbitrations
15.8 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC generation/checking, and error
detection. The protocol handler conforms to SAE J1850 – Class B Data Communications Network
Interface.
15.8.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx shadow register, Rx shift
register, Tx shift register, and loopback multiplexer as shown in Figure 15-11.
15.8.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus and makes them available in
parallel form to the Rx shadow register. The Tx shift register takes data, in parallel form, from the Tx
shadow register and presents it serially to the state machine so that it can be transmitted onto the J1850
bus.
15.8.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of data, this data is transferred to
the Rx shadow register and RDRF or RXIFR is set (see 15.9.3 BDLC State Vector Register). An interrupt
is generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer takes place, this new data
byte in the Rx shadow register is available to the CPU interface, and the Rx shift register is ready to shift
in the next byte of data. Data in the Rx shadow register must be retrieved by the CPU before it is
overwritten by new data from the Rx shift register.
TRANSMITTER A
TRANSMITTER B
J1850 BUS
SOF
DATA
BIT 1
DATA
BIT 4
DATA
BIT 5
0
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
TRANSMITTER B WINS
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
0
0
1
1
1
DATA
BIT 2
1
1
1
DATA
BIT 3
0
0
0
0
1
ARBITRATION AND
CONTINUES
TRANSMITTING