Datasheet

Byte Data Link Communications (BDLC)
M68HC12B Family Data Sheet, Rev. 9.1
238 Freescale Semiconductor
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR register except when the BDLC data register
needs servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can only be cleared by a read
of the BSVR register followed by a read of BDR. TDRE can either be cleared by a read of the BSVR
register followed by a write to the BDLC BDR register, or by setting the TEOD bit in BCR2. Clearing
an invalid symbol flag requires an EOF flag to be received before the BDLC can receive or transmit. If
ALOOP or DLOOP in BCR2 is set, the BDLC node is disengaged from the J1850 bus. Therefore, the
BDLC does not receive any data from the J1850 bus which normally generates BSVR flags.
Upon receiving a BDLC interrupt, the user may read the value within the BSVR, transferring it to the
CPU’s index register. The value can be used to index a jump table to access a service routine. For
example:
SERVICE LDX BSVR Fetch State Vector Number
JMP JMPTAB,XEnter service routine,
* (must end in an RTI)
*
JMPTAB JMP SERVE0Service condition #0
NOP
JMP SERVE1Service condition #1
NOP
JMP SERVE2Service condition #2
NOP
.
.
.
JMP SERVE8Service condition #8
END
NOTE
NOP instructions are used only to align the JMP instructions onto 4-byte
boundaries so that the value in the BSVR can be used intact. Each of the
service routines must end with an RTI instruction to guarantee correct
continued operation of the device. The first entry can be omitted since it
does not correspond to an interrupt.
Table 15-4. Interrupt Sources
BSVR I3 I2 I1 I0 Interrupt Source Priority
$00 0 0 0 0 No interrupts pending
0
(lowest)
$04 0001 Received EOF 1
$08 0 0 1 0 Received IFR byte (RXIFR) 2
$0C 0 0 1 1 BDLC Rx data register full (RDRF) 3
$10 0 1 0 0 BDLC Tx data register empty (TDRE) 4
$14 0 1 0 1 Loss of arbitration 5
$18 0 1 1 0 Cyclical redundancy check (CRC) error 6
$1C 0 1 1 1 Symbol invalid or out of range 7
$20 1 0 0 0 Wakeup 8 (highest)