Datasheet

BDLC Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 241
15.9.6 Port DLC Control Register
Read: Anytime
Write: Anytime
The BDLC port DLC functions as a general-purpose I/O port. BDLC functions takes precedence over the
general-purpose port when enabled.
BDLCEN — BDLC Enable Bit
1 = Configure I/O pins for BDLC function. BDLC is active.
0 = Configure BDLC I/O pins as general-purpose I/O. BDLC is off.
PUPDLC — BDLC Pullup Enable Bit
1 = Connects internal pullups to PORTDLC I/O pins
0 = Disconnects internal pullups from PORTDLC I/O pins
RDPDLC — BDLC Reduced Drive Bit
1 = Configure PORTDLC I/O pins for reduced drive strength.
0 = Configure PORTDLC I/O pins for normal drive strength.
Table 15-5. Offset Bit Values and Transceiver Delay
BO3–BO0 Expected Delay (µs)
0000 9
0001 10
0010 11
0011 12
0100 13
0101 14
0110 15
0111 16
1000 17
1001 18
1010 19
1011 20
1100 21
1101 22
1110 23
1111 24
Address: $00FD
Bit 7654321Bit 0
Read: 0 0 0 0 0
BDLCEN PUPDLC RDPDLC
Write:
Reset:00000000
= Unimplemented
Figure 15-18. Port DLC Control Register (DLCSCR)