Datasheet

Byte Data Link Communications (BDLC)
M68HC12B Family Data Sheet, Rev. 9.1
242 Freescale Semiconductor
15.9.7 Port DLC Data Register
Read: Anytime
Write: Anytime
This register holds data to be driven out on port DLC pins or data received from port DLC pins.
When configured as an input, a read returns the pin level. When configured as output, a read returns the
latched output data.
Writes do not change pin state when the pins are configured for BDLC output. Upon reset, pins are
configured for general-purpose high impedance inputs.
15.9.8 Port DLC Data Direction Register
Read: Anytime
Write: Anytime
DDDLC6–DDDLC0 — Data Direction Port DLC Bits
1 = Configure I/O pin for output
0 = Configure I/O pin for input only
Address: $00FE
Bit 7654321Bit 0
Read: 0
Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:0UUUUUUU
Alternate Pin Function: DLCTX DLCRX
= Unimplemented U = Unaffected
Figure 15-19. Port DLC Data Register (PORTDLC)
Address: $00FF
Bit 7654321Bit 0
Read: 0
DDDLC6 DDDLC5 DDDLC4 DDDLC3 DDDLC2 DDDLC1 DDDLC0
Write:
Reset:00000000
= Unimplemented
Figure 15-20. Port DLC Data Direction Register (DDRDLC)