Datasheet

msCAN12 Controller
M68HC12B Family Data Sheet, Rev. 9.1
244 Freescale Semiconductor
Figure 16-1. Typical CAN System with msCAN12
16.3.1 Background
Modern application layer software is built on two fundamental assumptions:
1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus
between two messages. Such nodes will arbitrate for the bus right after sending the previous
message and will only release the bus in case of lost arbitration.
2. The internal message queue within any CAN node is organized so that the highest priority
message will be sent out first if more than one message is ready to be sent.
This behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after
the previous message has been sent. This loading process lasts a definite amount of time and has to be
completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages.
Even if this is feasible for limited CAN bus speeds, it requires that the central processor unit (CPU) reacts
with short latencies to the transmit interrupt.
A double buffer scheme would decouple the reloading of the transmit buffers from the actual message
being sent and as such reduces the reaction requirements on the CPU. Problems may arise if the sending
of a message would be finished just while the CPU reloads the second buffer. In that case, no buffer would
then be ready for transmission and the bus would be released.
At least three transmit buffers are required to meet the first requirement under all circumstances. The
msCAN12 has three transmit buffers.
The second requirement calls for some sort of internal priorization which the msCAN12 implements with
the “local priority” concept described here.
CAN
msCAN12
CAN STATION 1
CAN STATION 2 CAN STATION N
TxCAN RxCAN
CAN SYSTEM
TRANSCEIVER
. . .
CONTROLLER