Datasheet

msCAN12 Controller

M68HC12B Family Data Sheet, Rev. 9.1

248 Freescale Semiconductor

2. Four identifier acceptance filters, each to be applied to:

a. 11 bits of the identifier and the RTR bit of CAN 2.0A messages, or

b. 14 most significant bits of the identifier of CAN 2.0B messages

Figure 16-4 shows how the first 32-bit filter bank (CIDAR0–CIDAR3, CIDMR0–CIDMR3) produces

filter 0 and 1 hit. Similarly, the second filter bank (CIDAR4–CUIDAR7, CIDMR4–CIDMR7)

produces filter 2 and three hits.

Figure 16-4. 16-Bit Maskable Acceptance Filters

3. Eight identifier acceptance filters, each to be applied to the first eight bits of the identifier. This

mode implements eight independent filters for the first eight bits of a CAN 2.0A compliant standard

identifier or of a CAN 2.0B compliant extended identifier. Figure 16-5 shows how the first 32-bit filter

bank (CIDAR0–CIDAR3, CIDMR0–CIDMR3) produces filter 0 to three hits. Similarly, the second

filter bank (CIDAR4–CUIDAR7, CIDMR4–CIDMR7) produces filter 4 to seven hits.

4. Closed filter. No CAN message will be copied into the foreground buffer RxFG, and the RXF flag

will never be set.

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AC7

IDR0

IDR1

IDR2 IDR3

AC0 AC7 AC0

AC7 AC0 AC7 AC0

CIDMRO CIDMR1

CIDAR1CIDARO

ID accepted (Filter 0 hit)

ID accepted (Filter 1 hit)

AC7 AC0 AC7 AC0

CIDMR2 CIDMR3

CIDAR3CIDAR2