Datasheet

Protocol Violation Protection
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 251
16.6 Protocol Violation Protection
The msCAN12 will protect the user from accidentally violating the CAN protocol through programming
errors. The protection logic implements these features:
• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers which control the configuration of the msCAN12 cannot be modified while
the msCAN12 is online. The SFTRES bit in CMCR0 (see 16.12.1 msCAN12 Module Control
Register 0) serves as a lock to protect these registers:
– msCAN12 module control register 1 (CMCR1)
– msCAN12 bus timing register 0 and 1 (CBTR0 and CBTR1)
– msCAN12 identifier acceptance control register (CIDAC)
– msCAN12 identifier acceptance registers (CIDAR0–CIDAR7)
– msCAN12 identifier mask registers (CIDMR0–CIDMR7)
• The TxCAN pin is forced to recessive if the CPU goes into stop mode.
16.7 Low-Power Modes
In addition to normal mode, the msCAN12 has three modes with reduced power consumption compared
to normal mode. In sleep and soft-reset mode, power consumption is reduced by stopping all clocks
except those to access the registers. In power-down mode, all clocks are stopped and no power is
consumed.
The wait-for-interrupt (WAI) and STOP instructions put the MCU in low power-consumption standby
modes. Table 16-2 summarizes the combinations of msCAN12 and CPU modes. A particular combination
of modes is entered for the given settings of the bits CSWAI, SLPAK, and SFTRES. For all modes, an
msCAN wakeup interrupt can occur only if SLPAK = WUPIE = 1. While the CPU is in wait mode, the
msCAN12 can be operated in normal mode and emit interrupts. (Registers can be accessed via
background debug mode.)
Table 16-1. msCAN12 Interrupt Vectors
Function Source
Local
Mask
Global
Mask
Wakeup WUPIF WUPIE
I bit
Error interrupts
RWRNIF RWRNIE
TWRNIF TWRNIE
RERRIF RERRIE
TERRIF TERRIE
BOFFIF BOFFIE
OVRIF OVRIE
Receive RXF RXFIE
Transmit
TXE0 TXEIE0
TXE1 TXEIE1
TXE2 TXEIE2