Datasheet

msCAN12 Controller
M68HC12B Family Data Sheet, Rev. 9.1
264 Freescale Semiconductor
CLKSRC — msCAN12 Clock Source Flag
This flag defines which clock source the msCAN12 module is driven from (only for system with CGM
module. See 16.9 Clock System and Figure 16-7.
0 = msCAN12 clock source is EXTALi.
1 = msCAN12 clock source is twice the frequency of ECLK.
NOTE
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is set.
16.12.3 msCAN12 Bus Timing Register 0
SJW1 and SJW0 — Synchronization Jump Width Bits
The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the
bus (see Table 16-5).
BRP5–BRP0 — Baud Rate Prescaler Bits
These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing,
according to Table 16-6.
NOTE
The CBTR0 register can be written only if the SFTRES bit in CMCR0 is set.
Address: $0102
Bit 7654321Bit 0
Read:
SJW1 SJW0 BRP5 BRP4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
Figure 16-18. msCAN12 Bus Timing Register 0 (CBTR0)
Table 16-5. Synchronization Jump Width
SJW1 SJW0 Synchronization Jump Width
0 0 1 Tq clock cycle
0 1 2 Tq clock cycles
1 0 3 Tq clock cycles
1 1 4 Tq clock cycles
Table 16-6. Baud Rate Prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler Value (P)
000000 1
000001 2
000010 3
000011 4
:::::: :
111111 64