Datasheet

Programmer’s Model of Control Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 265
16.12.4 msCAN12 Bus Timing Register 1
SAMP — Sampling Bit
This bit determines the number of samples of the serial bus to be taken per bit time. If set, three
samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority
rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken
per bit.
0 = One sample per bit
1 = Three samples per bit.
(1)
TSEG22–TSEG10 — Time Segment Bits
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. See Figure 16-7.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 16-8.
Address: $0103
Bit 7654321Bit 0
Read:
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Write:
Reset:00000000
Figure 16-19. msCAN12 Bus Timing Register 1 (CBTR1)
1. In this case, PHASE_SEG1 must be at least two times quanta.
Table 16-7. Time Segment Syntax
SYNC_SEG System expects transitions to occur on the bus during this period.
Transmit point A node in transmit mode will transfer a new value to the CAN bus at this point.
Sample point
A node in receive mode will sample the bus at this point. If the three samples per bit option is
selected, then this point marks the position of the third sample.
Table 16-8. Time Segment Values
TSEG13 TSEG12 TSEG11 TSEG10 Time Segment 1
0 0 0 0 1 Tq clock cycle
0 0 0 1 2 Tq clock cycles
0 0 1 0 3 Tq clock cycles
0 0 1 1 4 Tq clock cycles
.... .
1 1 1 1 16 Tq clock cycles
TSEG22 TSEG21 TSEG20 Time Segment 2
0 0 0 1 Tq clock cycle
0 0 1 2 Tq clock cycles
... .
1 1 1 8 Tq clock cycles