Datasheet

msCAN12 Controller
M68HC12B Family Data Sheet, Rev. 9.1
272 Freescale Semiconductor
16.12.11 msCAN12 Transmit Error Counter
This register reflects the status of the msCAN12 transmit error counter. The register is read only.
NOTE
Both error counters may be read only when in sleep or soft-reset mode.
16.12.12 msCAN12 Identifier Acceptance Registers
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit-by-bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are applied.
Address: $010F
Bit 7654321Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Reset:00000000
= Unimplemented
Figure 16-26. msCAN12 Transmit Error Counter (CTXERR)
Address: $0110
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
Address: $0111
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
Address: $0112
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
Address: $0113
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
Figure 16-27. First Bank msCAN12 Identifier Acceptance
Registers (CIDAR0–CIDAR3)