Datasheet

Programmer’s Model of Control Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 275
AM7–AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match will be detected. The message
will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit
in the identifier acceptance register will not affect whether or not the message is accepted.
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
NOTE
The CIDMR0–CIDMR7 registers can be written only if the SFTRES bit in
CMCR0 is set.
16.12.14 msCAN12 Port CAN Control Register
These bits control pins 7–2 of port CAN control register. Pins 1 and 0 are reserved for the RxCAN (input
only) and TxCAN (output only) pins.
PUECAN — Pullup Enable Port CAN Bit
0 = Pull mode disabled for port CAN
1 = Pull mode enabled for port CAN
RDPCAN — Reduced Drive Port CAN
0 = Reduced drive disabled for port CAN
1 = Reduced drive enabled for port CAN
16.12.15 msCAN12 Port CAN Data Register
PCAN7–PCAN2 — Port CAN Data Bits
Writing to PCANx stores the bit value in an internal bit memory. This value is driven to the respective
pin only if DDRCANx = 1.
Reading PCANx returns:
• Value of the internal bit memory driven to the pin, if DDRCANx = 1
• Value of the respective pin, if DDRCANx = 0
Reading bits 1 and 0 returns the value of the TxCAN and RxCAN pins, respectively.
Address: $013D
Bit 7654321Bit 0
Read:000000
PUECAN RDPCAN
Write:
Reset:00000000
= Unimplemented
Figure 16-31. msCAN12 Port CAN Control Register (PCTLCAN)
Address: $013E
Bit 7654321Bit 0
Read:
PCAN7 PCAN6 PCAN5 PCAN4 PCAN2 PCAN2
TxCAN RxCAN
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 16-32. msCAN12 Port CAN Data Register (PORTCAN)