Datasheet

Analog-to-Digital Converter (ATD)
M68HC12B Family Data Sheet, Rev. 9.1
282 Freescale Semiconductor
Clearing these bits causes the prescale value to default to 1 which results in a divide-by-two prescale
factor. This signal is then fed into the divide-by-two logic. The reset state divides the P clock by a total
of four and is appropriate for nominal operation at a bus rate of between 2 MHz and 8 MHz. Table 17-3
shows the divide-by operation and the appropriate range of system clock frequencies.
17.3.6 ATD Control Register 5
Read: Anytime
Write: Anytime
The ATD control register 5 is used to select the conversion modes, the conversion channel(s), and initiate
conversions.
A write to ATDCTL5 initiates a new conversion sequence. If a conversion sequence is in progress when
a write occurs, that sequence is aborted and the SCF and CCF bits are reset.
S8CM — Select 8 Channel Mode Bit
0 = Conversion sequence consists of four conversions.
1 = Conversion sequence consists of eight conversions.
Table 17-3. Clock Prescaler Values
Prescale Value Total Divisor
Max P Clock
(1)
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value becomes
maximum conversion rate that can be used on this ATD module.
Min P Clock
(2)
2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value becomes
minimum conversion rate that this ATD can perform.
00000 2 4 MHz 1 MHz
00001 4 8 MHz 2 MHz
00010 6 8 MHz 3 MHz
00011 8 8 MHz 4 MHz
00100 10 8 MHz 5 MHz
00101 12 8 MHz 6 MHz
00110 14 8 MHz 7 MHz
00111 16 8 MHz 8 MHz
01xxx
Do not use
1xxxx
Address: $0065
Bit 7654321Bit 0
Read:
S8CM SCAN MULT CD CC CB CA
Write:
Reset:00000000
= Unimplemented
Figure 17-7. ATD Control Register 5 (ATDCTL5)