Datasheet

ATD Registers
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 283
SCAN — Enable Continuous Channel Scan Bit
When a conversion sequence is initiated by a write to the ATDCTL register, the user has a choice of
performing a sequence of four (or eight, depending on the S8CM bit) conversions or continuously
performing four (or eight) conversion sequences.
0 = Single conversion sequence
1 = Continuous conversion sequences (scan mode)
MULT — Enable Multichannel Conversion Bit
0 = ATD sequencer runs all four or eight conversions on a single input channel selected via the CD,
CC, CB, and CA bits.
1 = ATD sequencer runs each of the four or eight conversions on sequential channels in a specific
group. Refer to Table 17-4.
CD, CC, CB, and CA — Channel Select for Conversion Bits
Table 17-4. Multichannel Mode Result Register Assignment
S8CM CD CC CB CA Channel Signal
Result in ADRx
if MULT = 1
000
0 0AN0 ADR0
0 1AN1 ADR1
1 0AN2 ADR2
1 1AN3 ADR3
001
0 0AN4 ADR0
0 1AN5 ADR1
1 0AN6 ADR2
1 1AN7 ADR3
010
0 0Reserved ADR0
0 1Reserved ADR1
1 0Reserved ADR2
1 1Reserved ADR3
011
0 0
V
RH
ADR0
0 1
V
RL
ADR1
1 0
(V
RH
+ V
RL
)/2
ADR2
1 1Test/reserved ADR3
10
0 0 0AN0 ADR0
0 0 1AN1 ADR1
0 1 0AN2 ADR2
0 1 1AN3 ADR3
1 0 0AN4 ADR4
1 0 1AN5 ADR5
1 1 0AN6 ADR6
1 1 1AN7 ADR7