Datasheet

M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 289
Chapter 18
Development Support
18.1 Introduction
Development support involves complex interactions between MCU resources and external development
systems. This section concerns instruction queue and queue tracking signals, background debug mode,
breakpoints, and instruction tagging.
18.2 Instruction Queue
It is possible to monitor CPU activity on a cycle-by-cycle basis for debugging.The CPU12 instruction
queue provides at least three bytes of program information to the CPU when instruction execution begins.
The CPU12 always completely finishes executing an instruction before beginning to execute the next
instruction. Status signals IPIPE1 and IPIPE0 provide information about data movement in the queue and
indicate when the CPU begins to execute instructions. Information available on the IPIPE1 and IPIPE0
pins is time multiplexed. External circuitry can latch data movement information on rising edges of the
E-clock signal; execution start information can be latched on falling edges. Table 18-1 shows the meaning
of data on the pins.
Table 18-1. IPIPE Decoding
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock
(1)
1. Refers to data that was on the bus at the previous E falling edge.
IPIPE[1:0] Mnemonic Meaning
0:0 — No movement
0:1 LAT Latch data from bus
1:0 ALD Advance queue and load from bus
1:1 ALL Advance queue and load from latch
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock
(2)
2. Refers to bus cycle starting at this E falling edge.
IPIPE[1:0] Mnemonic Meaning
0:0 — No start
0:1 INT Start interrupt sequence
1:0 SEV Start even instruction
1:1 SOD Start odd instruction