Datasheet

Background Debug Mode (BDM)
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 293
18.3.3 BDM Commands
All BDM command opcodes are eight bits long and can be followed by an address and/or data, as
indicated by the instruction. These commands do not require the CPU to be in active BDM for execution.
The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another
command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data
read commands, the host must insert this delay between sending the address and attempting to read the
data.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation
requires multiple cycles, CPU clocks are frozen until the operation is complete.
The two types of BDM commands are:
• Hardware
• Firmware
Hardware commands allow target system memory to be read or written. Target system memory includes
all memory that is accessible by the CPU12 including on-chip RAM, EEPROM, on-chip I/O and control
registers, and external memory connected to the target HC12 MCU. Hardware commands are
implemented in hardware logic and do not require the HC12 MCU to be in BDM mode for execution. The
control logic watches the CPU12 buses to find a free bus cycle to execute the command so that the
background access does not disturb the running application programs. If a free cycle is not found
within 128 E-clock cycles, the CPU12 is momentarily frozen so the control logic can steal a cycle. Refer
to Table 18-2 for commands implemented in BDM control logic.
Table 18-2. BDM Hardware Commands
Command Opcode (Hex) Data Description
BACKGROUND 90 None Enter background mode (if firmware enabled).
READ_BD_BYTE E4
16-bit address
16-bit data out
Read from memory with BDM in map (may steal cycles if
external access) data for odd address on low byte, data for even
address on high byte.
STATUS
(1)
E4
FF01,
0000 0000 (out)
READ_BD_BYTE $FF01. Running user code. (BGND
instruction is not allowed.)
FF01,
1000 0000 (out)
READ_BD_BYTE $FF01. BGND instruction is allowed.
FF01,
1100 0000 (out)
READ_BD_BYTE $FF01. Background mode active (waiting for
single wire serial command).
READ_BD_WORD EC
16-bit address
16-bit data out
Read from memory with BDM in map (may steal cycles if
external access) must be aligned access.
READ_BYTE E0
16-bit address
16-bit data out
Read from memory with BDM out of map (may steal cycles if
external access) data for odd address on low byte, data for even
address on high byte.
READ_WORD E8
16-bit address
16-bit data out
Read from memory with BDM out of map (may steal cycles if
external access) must be aligned access.
WRITE_BD_BYTE C4
16-bit address
16-bit data in
Write to memory with BDM in map (may steal cycles if external
access) data for odd address on low byte, data for even address
on high byte.
ENABLE_
FIRMWARE
(2)
C4
FF01,
1xxx xxxx (in)
Write byte $FF01, set the ENBDM bit. This allows execution of
commands which are implemented in firmware. Typically, read
STATUS, OR in the MSB, write the result back to STATUS.