Datasheet

Instruction Tagging
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 305
Table 18-10 shows the functions of the two tagging pins. The pins operate independently; the state of one
pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of ECLK
performs the indicated function. Tagging is allowed in all modes. Tagging is disabled when BDM becomes
active and BDM serial commands are not processed while tagging is active.
The tag follows the information in the queue as the queue is advanced. When a tagged instruction
reaches the head of the queue, the CPU enters active background debug mode rather than executing the
instruction. This is the mechanism by which a development system initiates hardware breakpoints.
Currently, the tool configuration shown in Figure 18-16 is used.
Figure 18-16. BDM Tool Connector
Table 18-10. Tag Pin Function
TAGHI TAGLO Tag
1 1 No tag
10 Low byte
0 1 High byte
0 0 Both bytes
2
4
65
3
1
RESET
BKGD
V
DD
GND
V
FP
NC