Datasheet

Pinout and Signal Descriptions
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 31
Table 1-3. Signal Description Summary
Pin
Name
Pin
Number
Description
PW3–PW0 3–6 Pulse-width modulator channel outputs
ADDR7–ADDR0
DATA7–DATA0
25–18
External bus pins share function with general-purpose I/O ports A and B. In single-chip
modes, the pins can be used for I/O. In expanded modes, the pins are used for the
external buses.
ADDR15–ADDR8
DATA15–DATA8
46–39
IOC7–IOC0 16–12, 9–7
Pins used for input capture and output compare in the timer and pulse accumulator
subsystem
PAI 16 Pulse accumulator input
AN7–AN0 58–51 Analog inputs for the analog-to-digital conversion module
DBE
26
Data bus control and, in expanded mode, enables the drive control of external buses
during external reads
MODB, MODA 27, 28 State of mode select pins during reset determines the initial operating mode of the
MCU. After reset, MODB and MODA can be configured as instruction queue tracking
signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
IPIPE1, IPIPE0 27, 28
ECLK 29
E-clock is the output connection for the external bus clock. ECLK is used as a timing
reference and for address demultiplexing.
RESET 32
An active low bidirectional control signal, RESET
acts as an input to initialize the MCU
to a known startup state and an output when COP or clock monitor causes a reset.
EXTAL 33
Crystal driver and external clock input pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
XTAL 34
LSTRB
35
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The low
strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. The SZ8
internal signal indicates the size 16/8 access.
TAG LO
35 Pin used in instruction tagging
R/W
36
Indicates direction of data on expansion bus; shares function with general-purpose I/O;
read/write in expanded modes
IRQ
37
Maskable interrupt request input provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge-sensitive triggering or level-sensitive
triggering is program selectable (INTCR register).
XIRQ
38
Provides a means of requesting asynchronous non-maskable interrupt requests after
reset initialization
BKGD 17
Single-wire background interface pin is dedicated to the background debug function.
During reset, this pin determines special or normal operating mode.
TAGHI 17 Pin used in instruction tagging
DLCRx/RxCAN
(1)
1. The RxCAN and TxCAN designations are for the MC68HC(9)12BC32 only.
76 BDLC receive pin
DLCTx/TxCAN
(1)
75 BDLC transmit pin
CS
/SS 68 Slave-select output for SPI master mode; input for slave mode or master mode
SCK 67 Serial clock for SPI system
SDO/MOSI 66 Master out/slave in pin for serial peripheral interface
SDI/MISO 65 Master in/slave out pin for serial peripheral interface
TxD0 62 SCI transmit pin
RxD0 61 SCI receive pin