Datasheet

FLASH EEPROM Characteristics
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 315
19.12.1 Programming Voltage Supply Envelope
The key to preventing damage to the FLASH array or corruption of the data contained in the memory is
the programming voltage envelope shown in Figure 19-1. Many of the problems that customers
experience with FLASH devices are due to a failure to ensure that their voltage sources always meet
these requirements.
The most important single thing to remember from this diagram is that V
FP
and V
DD
should always be at
the same level, except during an actual program or erase cycle. Corruption of FLASH data is often
encountered when V
FP
is allowed to exceed V
DD
during the power-up and power-down phases.
Conversely, if V
FP
is allowed to fall below 0.35 volts lower than V
DD
at any time, damage to the FLASH
array can occur.
NOTE
Although Figure 19-1 shows a lower boundary of 4.15 volts on V
FP
during
the normal read phase, V
FP
always must be no more than .35 volts below
V
DD
. For example, If the operating voltage of V
DD
in the system is 5.2 volts,
V
FP
can be no lower than 4.85 volts.
Figure 19-1. Programming Voltage Envelope
13.5 V
12.6 V
11.4 V
5.5 V
4.5 V
4.15 V
0 V
–0.30 V
V
FP
ENVELOPE
V
DD
ENVELOPE
COMBINED V
DD
AND V
FP
30 ns MAXIMUM
t
ER
PROGRAM
ERASE
POWER
DOWN
POWER
UP
NORMAL
READ