Datasheet

Electrical Specifications
M68HC12B Family Data Sheet, Rev. 9.1
326 Freescale Semiconductor
19.16 Multiplexed Expansion Bus Timing
NOTE
Use of the multiplexed expansion bus at 8 MHz is discouraged due to TAD
delay factors.
Num
Characteristic
(1), (2), (3), (4), (5)
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted
2. All timings are calculated for normal port drives.
3. Crystal input is required to be within 45% to 55% duty.
4. Reduced drive must be off to meet these timings.
5. Unequalled loading of pins will affect relative timing numbers.
Delay Symbol
8 MHz 2 MHz
Unit
Min Max Min Max
— Frequency of operation (E-clock frequency) —
f
o
dc 8.0 dc 8.0 MHz
1
Cycle timet
cyc
= 1/f
o
—
t
cyc
125 — 500 — ns
2
Pulse width, E lowPW
EL
= t
cyc
/2 + delay
−4
PW
EL
59 — 246 — ns
3
Pulse width, E high
(6)
PW
EH
= t
cyc
/2 + delay
6. This characteristic is affected by clock stretch.
Add N × t
cyc
where N = 0, 1, 2, or 3, depending on the number of clock stretches.
−2
PW
EH
59 — 248 — ns
5
Address delay timet
AD
= t
cyc
/4 + delay
27
t
AD
— 67.5 — 152 ns
7
Address valid time to ECLK riset
AV
= PW
EL
− t
AD
—
t
AV
–6.2 — 94 — ns
8
Multiplexed address hold timet
MAH
= t
cyc
/4 + delay
−18
t
MAH
13 — 107 — ns
9 Address hold to data valid —
t
AHDS
30 — 20 — ns
10
Data hold to high impedancet
DHZ
= t
AD
− 20
—
t
DHZ
— 45.2 — 132 ns
11 Read data setup time —
t
DSR
31.2 — 25 — ns
12 Read data hold time —
t
DHR
0—0—ns
13 Write data delay time —
t
DDW
— 62.5 — 165 ns
14 Write data hold time —
t
DHW
25 — 20 — ns
15
Write data setup time
(6)
t
DSW
= PW
EH
− t
DDW
—
t
DSW
5.8 — 83 — ns
16
Read/write delay timet
RWD
= t
cyc
/4 + delay
18
t
RWD
— 57.5 — 143 ns
17
Read/write valid time to E riset
RWV
= PW
EL
− t
RWD
—
t
RWV
3.8 — 103 — ns
18 Read/write hold time —
t
RWH
25 — 20 — ns
19
Low strobe
(7)
delay timet
LSD
= t
cyc
/4 + delay
7. Without TAG enabled
18
t
LSD
— 57.5 — 143 ns
20
Low strobe
(7)
valid time to E riset
LSV
= PW
EL
− t
LSD
—
t
LSV
3.8 — 103 — ns
21
Low strobe
(7)
hold time
—
t
LSH
25 — 20 — ns
22
Address access time
(6)
t
ACCA
= t
cyc
− t
AD
− t
DSR
—
t
ACCA
— 27.6 — 323 ns
23
Access time from E rise
(6)
t
ACCE
= PW
EH
− t
DSR
—
t
ACCE
— 27.8 — 223 ns
24
DBE
delay from ECLK rise
(6)
t
DBED
= t
cyc
/4 + delay
8
t
DBED
— 57.5 — 133 ns
25
DBE
valid timet
DBE
= PW
EH
− t
DBED
—
t
DBE
11.8 — 115 — ns
26 DBE
hold time from ECLK fall —
t
DBEH
–3 10 –3 10 ns