Datasheet

Serial Peripheral Interface (SPI) Timing
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor 329
Figure 19-13. SPI Master Timing Diagram
SCK
OUTPUT
SCK
OUTPUT
MISO
INPUT
MOSI
OUTPUT
SS
(1)
OUTPUT
1
10
6 7
MSB IN
(2)
BIT 6 . . . 1
LSB IN
MSB OUT
(2)
LSB OUT
BIT 6 . . . 1
11
4
4
2
10
CPOL = 0)
CPOL
= 1
5
3
12
13
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
A) SPI Master Timing (CPHA = 0)
B) SPI Master Timing (CPHA = 1)
SCK
OUTPUT
SCK
OUTPUT
MISO
INPUT
MOSI
OUTPUT
1
6 7
MSB IN
(2)
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
(2)
MASTER LSB OUT
BIT 6
. . . 1
4
4
10
12 13
11
PORT DATA
CPOL
= 0
CPOL
= 1
PORT DATA
SS
(1)
OUTPUT
5
2
13 12 3
1. SS
output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Notes:
Notes: