Datasheet

Central Processor Unit (CPU)
M68HC12B Family Data Sheet, Rev. 9.1
62 Freescale Semiconductor
3.3.5 Program Counter
The program counter contains the address of the next instruction to be executed.
The program counter can also serve as an index register in all indexed addressing modes except
autoincrement and autodecrement.
3.3.6 Condition Code Register
S — Stop Disable Bit
Setting the S bit disables the STOP instruction.
X — XIRQ Interrupt Mask Bit
Setting the X bit masks interrupt requests from the XIRQ
pin.
H — Half-Carry Flag
The H flag is used only for BCD arithmetic operations. It is set when an ABA, ADD, or ADC instruction
produces a carry from bit 3 of accumulator A. The DAA instruction uses the H flag and the C flag to
adjust the result to the correct BCD format.
I — Interrupt Mask Bit
Setting the I bit disables maskable interrupt sources.
N — Negative Flag
The N flag is set when the result of an operation is less than 0.
Z — Zero Flag
The Z flag is set when the result of an operation is all 0s.
V — Two’s Complement Overflow Flag
The V flag is set when a two’s complement overflow occurs.
C — Carry/Borrow Flag
The C flag is set when an addition or subtraction operation produces a carry or borrow.
Figure 3-8. Program Counter (PC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Read:
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Write:
Reset: Unaffected by reset
Bit 7654321Bit 0
Read:
SXH I NZVC
Write:
Reset:1 1U1UUUU
U = Unaffected
Figure 3-9. Condition Code Register (CCR)