Datasheet

Bus Control and Input/Output (I/O)
M68HC12B Family Data Sheet, Rev. 9.1
86 Freescale Semiconductor
be set. In this special case of expanded mode and EME set, the port E data register (PORTE) and port E
data direction register (DDRE) are removed from the on-chip memory map and become external
accesses so port E may be rebuilt externally.
6.3.1 Port A Data Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
Bits PA7–PA0 are associated with addresses ADDR15–ADDR8 and DATA15–DATA8. When this port is
not used for external addresses and data, such as in single-chip mode, these pins can be used as
general-purpose input/output (I/O). DDRA determines the primary direction of each pin. This register is
not in the on-chip map in expanded and peripheral modes.
6.3.2 Port A Data Direction Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
This register determines the primary direction for each port A pin when functioning as a general-purpose
I/O port. DDRA is not in the on-chip map in expanded and peripheral modes.
1 = Associated pin is an output.
0 = Associated pin is a high-impedance input.
Address:
$0000
Bit 7654321Bit 0
Read:
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by reset
Expanded wide and peripheral:
ADDR15
DATA15
ADDR14
DATA14
ADDR13
DATA13
ADDR12
DATA12
ADDR11
DATA11
ADDR10
DATA10
ADDR9
DATA9
ADDR8
DATA8
Expanded narrow:
ADDR15
DATA15/7
ADDR14
DATA14/6
ADDR13
DATA13/5
ADDR12
DATA12/4
ADDR11
DATA11/3
ADDR10
DATA10/2
ADDR9
DATA9/1
ADDR8
DATA8/0
Figure 6-1. Port A Data Register (PORTA)
Address:
$0002
Bit 7654321Bit 0
Read:
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
Write:
Reset:00000000
Figure 6-2. Port A Data Direction Register (DDRA)