Datasheet

Input/Output (I/O) Ports
MC68HC908JL3E Family Data Sheet, Rev. 4
112 Freescale Semiconductor
10.4.3 Port D Control Register (PDCR)
The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
SLOWDx — Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the Slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull
PTDPUx — Pull-up Enable
The PTDPU6 and PTDPU7 bits enable the 5kΩ pull-up on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Enable 5kΩ pull-up
0 = Disable 5kΩ pull-up
Table 10-4. Port D Pin Functions
DDRD
Bit
PTD Bit I/O Pin Mode
Accesses to
DDRD
Accesses to PTD
Read/Write Read Write
0X
(1)
1. X = don’t care.
Input, Hi-Z
(2)
2. Hi-Z = high impedance.
DDRD[7:0] Pin PTD[7:0]
(3)
3. Writing affects data register, but does not affect the input.
1 X Output DDRD[7:0] Pin PTD[7:0]
Address: $000A
Bit 7654321Bit 0
Read: 0 0 0 0
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Write:
Reset:00000000
= Unimplemented
Figure 10-12. Port D Control Register (PDCR)