Datasheet

Monitor ROM
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor 23
Addr.Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PTA)
Read: 0
PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PTB)
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002 Unimplemented
Read:
Write:
$0003
Port D Data Register
(PTD)
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
$0004
Data Direction Register A
(DDRA)
Read: 0
DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
$0006 Unimplemented
Read:
Write:
$0007
Data Direction Register D
(DDRD)
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
$0008
↓
$0009
Unimplemented
Read:
Write:
$000A
Port D Control Register
(PDCR)
Read:0000
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Write:
Reset:00000000
$000B
↓
$000C
Unimplemented
Read:
Write:
$000D
Port A Input Pull-up Enable
Register (PTAPUE)
Read:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
$000E
↓
$0019
Unimplemented
Read:
Write:
= Unimplemented R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 4)