Datasheet

MC68HC908JL3E Family Data Sheet, Rev. 4
4 Freescale Semiconductor
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
Description
Page
Number(s)
October 2006 4
Table 4-1. Instruction Set Summary — Updated table to include the
WAIT instruction.
42
5.7.1 Break Status Register (BSR) — Updated for clarity. 63
5.7.2 Reset Status Register (RSR) — Updated description for clarity. 64
7.4 Security — Updated to reflect the correct RAM location ($80) to
determine if the security code has been entered correctly.
80
8.9.1 TIM Status and Control Register (TSC) — Added note to definition
of TSTOP bit.
89
10.1 Introduction — Added note regarding 20-pin devices. 103
15.4.3 Break Status Register — Updated for clarity. 132
Chapter 17 Mechanical Specifications — Updated package drawings to
the latest available.
147
Nov 2004 3
Added appendix B for ROM parts. 159–166
Added appendix C for ADC-less parts. 167–170
Dec 2002 2
Added appendix A for low-volt devices. 153–224
Updated Monitor Mode Circuit (Figure 7-1) and Monitor Mode Entry
Requirements and Options (Table 7-1) in Monitor ROM section.
76, 77
May 2002 1 First general release. —