Datasheet

Exception Control
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor 59
5.5.2.1 Interrupt Status Register 1
IF1, IF3 to IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3 and 7 — Always read 0
5.5.2.2 Interrupt Status Register 2
Table 5-3. Interrupt Sources
Priority Source Flag
MASK
(1)
INT
Register
Flag
Vector Address
Highest Reset — — — $FFFE–$FFFF
SWI Instruction — — — $FFFC–$FFFD
IRQ
Pin IRQF IMASK IF1 $FFFA–$FFFB
Timer Channel 0 Interrupt CH0F CH0IE IF3 $FFF6–$FFF7
Timer Channel 1 Interrupt CH1F CH1IE IF4 $FFF4–$FFF5
Timer Overflow Interrupt TOF TOIE IF5 $FFF2–$FFF3
Keyboard Interrupt KEYF IMASKK IF14 $FFE0–$FFE1
Lowest ADC Conversion Complete Interrupt COCO AIEN IF15 $FFDE–$FFDF
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
Address: $FE04
Bit 7654321Bit 0
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 5-12. Interrupt Status Register 1 (INT1)
Address: $FE05
Bit 7654321Bit 0
Read:IF140000000
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 5-13. Interrupt Status Register 2 (INT2)