Datasheet

Monitor ROM (MON)
MC68HC908JL3E Family Data Sheet, Rev. 4
72 Freescale Semiconductor
Figure 7-1. Monitor Mode Circuit
NOTES:
1. Monitor mode entry method:
SW1: Position A — High voltage entry (V
TST
)
Clock source must be EXT OSC or XTAL CIRCUIT.
Bus clock depends on SW2.
SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)
Bus clock = OSC1 ÷ 4.
2. Affects high voltage entry to monitor mode only (SW1 at position A):
SW2: Position C — Bus clock = OSC1 ÷ 4
SW2: Position D — Bus clock = OSC1 ÷ 2
5. See Table 16-4. DC Electrical Characteristics (5V) for V
TST
voltage level requirements.
10M
RST
IRQ
OSC1
OSC2
V
SS
PTB0
20 pF
20 pF
0.1 μF
9.8304MHz
PTB1
V
DD
0.1 μF
V
DD
PTB2
V
DD
10 k
PTB3
V
DD
10 k
10 k
SW2
C
D
V
DD
(SEE NOTE 2)
A
B
XTAL CIRCUIT
16
15
2
6
V
DD
MAX232
V+
V–
V
DD
10 k
C1+
C1–
5
4
C2+
C2–
+
3
1
1 μF
+
+
+
8
7
DB9
2
3
5
10
9
+
1
2
3
4
5
6
74HC125
74HC125
1 k
V
TST
V
CC
GND
1 μF
1 μF
1 μF
1 μF
8.5 V
V
DD
10 k
10 k
(50% DUTY)
OSC1
(SEE NOTE 1)
SW1
V
DD
OSC1
OSC2
See Figure 16-1. RC vs. Frequency
(5V @25°C) for component values
vs. frequency.
H(R)C908JL3E
H(R)C908JK3E
H(R)C908JK1E
EXT OSC
OSC2
RC CIRCUIT
FOR MC68HC908JL3E/JK3E/JK1E
SW1 AT POSITION A OR B
FOR MC68HRC908JL3E/JK3E/JK1E
SW1 MUST BE AT POSITION A
FOR MC68HC908JL3E/JK3E/JK1E
SW1 AT POSITION A OR B
FOR MC68HRC908JL3E/JK3E/JK1E
SW1 MUST BE AT POSITION B