Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsMFRC53001T/0FE,112

1. Introduction

This data sheet describes the functionality of the MFRC530 Integrated Circuit (IC). It

includes the functional and electrical specifications and from a system and hardware

viewpoint gives detailed information on how to design-in the device.

Remark: The MFRC530 supports all variants of the MIFARE Classic, MIFARE 1K and

MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the

MIFARE Classic, MIFARE 1K and MIFARE 4K products and protocols have the generic

name MIFARE.

2. General description

The MFRC530 is highly integrated reader IC for contactless communication at 13.56 MHz.

The MFRC530 reader IC provides:

• outstanding modulation and demodulation for passive contactless communication

• a wide range of methods and protocols

• pin compatibility with the CLRC632, MFRC500, MFRC531 and SLRC400

All protocol layers of the ISO/IEC 14443 A are supported

The receiver module provides a robust and efficient demodulation/decoding circuitry

implementation for compatible transponder signals (see Section 9.10 on page 31

). The

digital module, manages the complete ISO/IEC 14443 A standard framing and error

detection (parity and CRC). In addition, it supports the fast Crypto1 security algorithm for

authenticating the MIFARE products (see Section 9.13 on page 37

The internal transmitter module (Section 9.9 on page 28

) can directly drive an antenna

designed for a proximity operating distance up to 100 mm without any additional active

circuitry.

A parallel interface can be directly connected to any 8-bit microprocessor to ensure

reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility

is supported (see Section 9.1.4 on page 9

MFRC530

Standard MIFARE reader solution

Rev. 3.4 — 12 February 2014

057434

Product data sheet

COMPANY PUBLIC

Summary of content (115 pages)

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MFRC530 Standard MIFARE reader solution Rev. 3.4 — 12 February 2014 057434 Product data sheet COMPANY PUBLIC 1. Introduction This data sheet describes the functionality of the MFRC530 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. Remark: The MFRC530 supports all variants of the MIFARE Classic, MIFARE 1K and MIFARE 4K RF identification protocols.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 3. Features and benefits 3.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 5. Quick reference data Table 1. Quick reference data Symbol Parameter Tamb Conditions Min Typ Max Unit ambient temperature 40 - +150 C Tstg storage temperature 40 - +150 C VDDD digital supply voltage 0.5 +5 +6 V VDDA analog supply voltage 0.5 +5 +6 V VDD(TVDD) TVDD supply voltage 0.5 +5 +6 V Vi input voltage (absolute value) on any digital pin to DVSS 0.5 - VDDD + 0.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 7.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 8. Pinning information OSCIN 1 32 OSCOUT IRQ 2 31 RSTPD MFIN 3 30 VMID MFOUT 4 29 RX TX1 5 28 AVSS TVDD 6 27 AUX TX2 7 26 AVDD TVSS 8 NCS 9 MFRC530 25 DVDD 24 A2 23 A1 NWR/R/NW/nWrite 10 22 A0/nWait NRD/NDS/nDStrb 11 21 ALE/AS/nAStrb DVSS 12 AD0/D0 13 20 D7/AD7 AD1/D1 14 19 D6/AD6 AD2/D2 15 18 D5/AD5 17 D4/AD4 AD3/D3 16 001aam353 Fig 2. MFRC530 pin configuration 8.1 Pin description Table 3.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 3.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The MFRC530 supports direct interfacing to various 8-bit microprocessors. Alternatively, the MFRC530 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows the parallel interface signals supported by the MFRC530. Table 4.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. Table 5. MFRC530 pins 9.1.3.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER DEVICE NCS non-multiplexed address ADDRESS DECODER LOW A2 HIGH address bus (A0 to A2) A1 LOW A0 to A2 data bus (D0 to D7) A0 multiplexed address/data (AD0 to AD7) AD0 to AD7 D0 to D7 HIGH Address strobe (AS) ALE Data strobe (NDS) Read/Write (R/NW) DEVICE NCS ALE Data strobe (NDS) NRD NRD Read/Write (R/NW) NWR NWR 001aak608 Fig 4.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 6. SPI compatibility MFRC530 pins SPI pins ALE NSS A2 SCK A1 LOW A0 MOSI NRD HIGH NWR HIGH NCS LOW D7 to D1 do not connect D0 MISO Figure 6 shows the microprocessor connection to the MFRC530 using SPI. DEVICE NCS LOW SCK A2 LOW A1 MOSI A0 MISO D0 NSS ALE 001aak610 Fig 6.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 8. SPI read address Address (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)[1] byte 0 1 address address address address address address reserved byte 1 to byte n reserved address address address address address address reserved byte n + 1 [1] 9.1.4.2 0 0 0 0 0 0 0 0 All reserved bits must be set to logic 0. SPI write data The structure shown in Table 9 must be used to write data using SPI.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.2 Memory organization of the EEPROM Table 11. EEPROM memory organization diagram Block MFRC530 Product data sheet COMPANY PUBLIC Byte address Access Memory content Refer to Position Address 0 0 00h to 0Fh R product information field Section 9.2.1 on page 13 1 1 10h to 1Fh R/W Section 9.2.2.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.2.1 Product information field (read only) Table 12. Product information field byte allocation Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol CRC Internal Product Serial Number - Product Type Identification Access R R R R R Table 13.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution The byte assignment is shown in Table 15. Table 15. 9.2.2.2 Byte assignment for register initialization at start-up EEPROM byte address Register address Remark 10h (block 1, byte 0) 10h skipped 11h 11h copied … … … 2Fh (block 2, byte 15) 2Fh copied Factory default StartUp register initialization file During the production tests, the StartUp register initialization file is initialized using the default values shown in Table 16.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 16.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is shown in Figure 7. Master key byte 0 (LSB) 1 5 (MSB) Master key bits k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0 k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0 k7 k6 k5 k4 k7 k6 k5 k4 k3 k2 k1 k0 k3 k2 k1 k0 EEPROM byte address n n+1 n+2 n+3 n + 10 n + 11 Example 5Ah F0h 5Ah E1h 5Ah A5h 001aak640 Fig 7.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution When the microprocessor starts a command, the MFRC530 can still access the FIFO buffer while the command is running. Only one FIFO buffer has been implemented which is used for input and output. Therefore, the microprocessor must ensure that there are no inadvertent FIFO buffer accesses. Table 18 gives an overview of FIFO buffer access during command processing. Table 18.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution HiAlert =  64 – FIFOLength   WaterLevel (1) The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or less are stored in the FIFO buffer. The trigger is generated by Equation 2: LoAlert = FIFOLength  WaterLevel (2) 9.3.4 FIFO buffer registers and flags Table 19 shows the related FIFO buffer flags in alphabetic order. Table 19.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 on page 17) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to logic 1. When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to logic 1. Table 20.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0 while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq to logic 1 and leaves all other bits unchanged. 9.4.3 Configuration of pin IRQ The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be controlled using the following IRQPinConfig register bits.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.5 Timer unit The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor can use this timer to manage timing-relevant tasks. The timer unit may be used in one of the following configurations: • • • • • Timeout counter WatchDog counter Stopwatch Programmable one shot Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific timed event occurred.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution TStartTxBegin TReloadValue[7:0] TxBegin Event TStartTxEnd PARALLEL IN TxEnd Event START COUNTER/ PARALLEL LOAD TAutoRestart TStartNow Q S COUNTER MODULE (x ≤ x − 1) TRunning Q R TStopNow STOP COUNTER RxEnd Event TStopRxEnd RxBegin Event TStopRxBegin TPreScaler[4:0] 13.56 MHz CLOCK DIVIDER PARALLEL OUT to parallel interface TimerValue[7:0] Counter = 0 ? to interrupt logic: TimerIRq 001aak611 Fig 8.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution • transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1 • transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1 • bit TStartNow is set to logic 1 by the microprocessor Remark: Every start event reloads the timer from the TimerReload register which re-triggers the timer unit.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event. If a given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. The status of all pins during a hard power-down is shown in Table 24. Table 24.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.7.3 Initialization phase The initialization phase automatically follows the reset phase and takes 128 clock cycles. During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the register subaddresses 10h to 2Fh (see Section 9.2.2 on page 13). Remark: During the production test, the MFRC530 is initialized with default configuration values. This reduces the microprocessor’s configuration time to a minimum. 9.7.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. It must meet the specifications described in Section 13.4.5 on page 95. Remark: We do not recommend using an external clock source. 9.9 Transmitter pins TX1 and TX2 The signal on pins TX1 and TX2 is the 13.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.9.3 Antenna driver output source resistance The output source conductance of pins TX1 and TX2 can be adjusted between 1  and 100  using the CwConductance register GsCfgCW[5:0] bits. The output source conductance of pins TX1 and TX2 during the modulation phase can be adjusted between 1  and 100  using the ModConductance register GsCfgMod[5:0] bits.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 27. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod …continued MANT = Mantissa; EXP= Exponent. GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, RS(ref) MANTGsCfgMod () (decimal) GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () 23 1 7 0.0745 59 3 11 0.0127 14 0 14 0.0714 60 3 12 0.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.10 Receiver circuit The MFRC530 uses an integrated quadrature demodulation circuit enabling it to extract the ISO/IEC 14443 A compliant subcarrier from the 13.56 MHz ASK modulated signal applied to pin RX. The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.10.2.1 Automatic Q-clock calibration The quadrature demodulation concept of the receiver generates a phase signal (I-clock) and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90. After the reset phase, a calibration procedure is automatically performed.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.10.2.2 Amplifier The demodulated signal must be amplified by the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted using the RxControl1 register Gain[1:0] bits; see Table 28. Table 28. Gain factors for the internal amplifier See Table 84 “RxControl1 register bit descriptions” on page 59 for additional information. 9.10.2.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Remark: It is recommended to use the Q-clock. 9.11 Serial signal switch The MFRC530 comprises two main blocks: • digital circuitry: comprising the state machines, encoder and decoder logic etc. • analog circuitry: comprising the modulator, antenna drivers, receiver and amplification circuitry The interface between these two blocks can be configured so that the interface signals are routed to pins MFIN and MFOUT.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution serial data out MILLER CODER 1 OUT OF 256 NRZ OR 1 OUT OF 4 0 0 1 1 envelope 2 MFIN 3 TX1 MODULATOR TX2 2 (part of) serial data processing internal 2 Manchester with subcarrier 3 Manchester 0 1 envelope transmit NRZ Manchester with subcarrier Manchester reserved reserved 2 3 4 5 6 7 Manchester out 1 MANCHESTER DECODER 0 1 0 serial data in (part of) analog circuitry Modulator Source[1:0] 0 2 SUBCARRIER DE
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 30. ModulatorSource[1:0] values See Table 94 on page 62 for additional information. Number ModulatorSource[1:0] Input signal to modulator 0 00 constant 0 (energy carrier off on pins TX1 and TX2) 1 01 constant 1 (continuous energy carrier on pins TX1 and TX2) 2 10 modulation signal (envelope) from the internal encoder. This is the default configuration.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Two MFRC530 devices configured as described in Table 32 can be connected to each other using pins MFOUT and MFIN. Remark: The active antenna concept can only be used at a baud rate of 106 kBd. 9.11.2.2 Driving both RF parts It is possible to connect both passive and active antennas to a single IC. The passive antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching circuit.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 9.13.1 Crypto1 key handling On execution of the authentication command, the MFRC530 reads the key from the key buffer. The key is always read from the key buffer and ensures Crypto1 authentication commands do not require addressing of a key. The user must ensure the correct key is prepared in the key buffer before triggering card authentication. The key buffer can be loaded from: • the EEPROM using the LoadKeyE2 command (see Section 11.6.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10. MFRC530 registers 10.1 Register addressing modes Three methods can be used to operate the MFRC530: • initiating functions and controlling data by executing commands • configuring the functional operation using a set of configuration bits • monitoring the state of the MFRC530 by reading status flags The commands, configuration bits and flags are accessed using the microprocessor interface.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers. Table 36 describes the function of the Access column in the register tables. Table 36. Behavior and designation of register bits Abbreviation Behavior Description R/W read and write These bits can be read and written by the microprocessor.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.3 Register overview Table 37.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 37.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.4 MFRC530 register flags overview Table 38.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 38.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 38.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. Table 39. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation Bit 10.5.1.2 7 6 5 4 Symbol UsePageSelect 0000 Access R/W R/W Table 40.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. Table 43. FIFOData register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 5 4 3 Symbol FIFOData[7:0] Access D Table 44. 10.5.1.4 6 2 1 0 FIFOData register bit descriptions Bit Symbol Description 7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 46.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.1.6 SecondaryStatus register Various secondary status flags. Table 49. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation Bit 7 6 5 Symbol TRunning E2Ready CRCReady 00 RxLastBits[2:0] Access R R R R R Table 50.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.1.8 InterruptRq register Interrupt request flags. Table 53. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 Symbol SetIRq 0 TimerIRq TxIRq RxIRq Access W R/W D D D Table 54.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 46. 10.5.2.2 Control register Various control flags, for timer, power saving, etc. Table 55. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation Bit 7 Product data sheet COMPANY PUBLIC 5 Symbol 00 StandBy Access R/W D Table 56.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.2.3 ErrorFlag register Error flags show the error status of the last executed command. Table 57. Bit 7 6 5 4 3 2 1 0 Symbol 0 KeyErr AccessErr FIFOOvfl CRCErr FramingErr ParityErr CollErr Access R R R R R R R R Table 58.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.2.4 CollPos register Bit position of the first bit-collision detected on the RF interface. Table 59. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 Symbol CollPos[7:0] Access R Table 60. 2 1 0 CollPos register bit descriptions Bit Symbol Description 7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a received frame.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.2.7 CRCResultMSB register MSB of the CRC coprocessor register. Table 65. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 Symbol CRCResultMSB[7:0] Access R Table 66. 1 0 CRCResultMSB register bit descriptions Bit Symbol Description 7 to 0 CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if CRCReady = logic 1.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 46. 10.5.3.2 TxControl register Controls the logical behavior of the antenna pins TX1 and TX2. Table 69.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. Table 71. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 Symbol 00 GsCfgCW[5:0] Access R/W R/W Table 72.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 75. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation Bit 7 6 4 3 2 1 Symbol 00 CoderRate[2:0] 001 Access R/W R/W R/W Table 76.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.3.7 PreSet16 register These bit settings must not be changed. Table 79. PreSet16 register (address: 16h) reset value: 0000 0000b, 00h bit allocation Bit 7 5 4 3 Symbol 00000000 Access R/W Table 80. Bit 2 1 0 PreSet16 register bit descriptions Symbol Value Description 7 to 0 00000000 10.5.3.8 6 0 these values must not be changed PreSet17 register These bit settings must not be changed. Table 81.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 46. 10.5.4.2 RxControl1 register Controls receiver operation. Table 83.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.4.3 DecoderControl register Controls decoder operation. Table 85. Bit DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit allocation 7 6 Symbol 0 Access R/W Table 86.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. Table 89. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation Bit 7 5 4 3 2 1 Symbol MinLevel[3:0] CollLevel[3:0] Access R/W R/W Table 90. 10.5.4.6 6 0 RxThreshold register bit descriptions Bit Symbol Description 7 to 4 MinLevel[3:0] the minimum signal strength the decoder will accept.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. Table 93. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation Bit 7 6 Symbol RcvClkSelI RxAutoPD 0000 DecoderSource[1:0] Access R/W R/W R/W R/W Table 94.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 46. 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. Table 97. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation Bit 7 5 4 3 Symbol RxWait[7:0] Access R/W Table 98. 10.5.5.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 100. ChannelRedundancy bit descriptions …continued Bit Symbol Value Function 1 ParityOdd 1 odd parity is generated or expected[2] 0 even parity is generated or expected 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (MIFARE, ISO/IEC 14443 A) 0 no parity bit is inserted or expected 0 10.5.5.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 106. PreSet25 register bit descriptions 10.5.5.7 Bit Symbol Value Description 7 to 0 00000000 0 these values must not be changed MFOUTSelect register Selects the internal signal applied to pin MFOUT. Table 107. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00000 MFOUTSelect[2:0] Access R/W R/W Table 108.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 46. 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. Table 111. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation Bit 7 6 5 4 3 2 Symbol 00 WaterLevel[5:0] Access R/W R/W 1 0 Table 112.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. Table 115. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin Access R/W R/W R/W R/W R/W Table 116.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. Table 119. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000000 IRQInv IRQPushPull Access R/W R/W R/W Table 120. IRQPinConfig register bit descriptions Bit Symbol Value Description 7 to 2 000000 0 these values must not be changed 1 IRQInv 0 10.5.6.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 46. 10.5.8.2 Reserved register 39h Table 124. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 Symbol xxxxxxxx Access W 2 1 0 Remark: This register is reserved for future use. 10.5.8.3 TestAnaSelect register Selects analog test signals. Table 125.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.8.4 Reserved register 3Bh Table 127. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 Symbol xxxxxxxx Access W 2 1 0 Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Table 128.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10.5.8.7 Reserved registers 3Eh, 3Fh Table 131. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 Symbol xxxxxxxx Access W 2 1 0 Remark: This register is reserved for future use. 11. MFRC530 command set MFRC530 operation is determined by an internal state machine capable of performing a command set. The commands can be started by writing the command code to the Command register.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 132. MFRC530 commands overview …continued Command Value Action FIFO communication Arguments and data sent Data received Transceive[1] 1Eh data stream transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11.2.3 on page 80.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.1.1 Basic states 11.1.2 StartUp command 3Fh Table 133. StartUp command 3Fh Command Value Action Arguments and data Returned data StartUp 3Fh runs the reset and initialization phase - - Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.2 Commands for card communication The MFRC530 is a fully ISO/IEC 14443 A compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE reader ICs. Section 11.2.1 to Section 11.2.5 describe the command set for ISO/IEC 14443 A card communication and related communication protocols. 11.2.1 Transmit command 1Ah Table 135.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A frame transmitted consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bits; see Section 11.2.4 on page 80.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution TxLastBits[2:0] TxLastBits = 0 FIFOLength[6:0] 01h 00h FIFO empty TxData 7 0 7 0 7 check FIFO empty accept further data 001aak619 Fig 16. Timing for transmitting byte oriented frames As long as the internal signal accept further data is logic 1, data can be written to the FIFO buffer. The MFRC530 appends this data to the data stream transmitted using the RF interface.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Figure 17 also shows write access to the FIFOData register just before the FIFO buffer’s status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function. This function verifies FIFO empty for one bit duration before the last expected bit transmission.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.2.2.2 RF channel redundancy and framing The decoder expects the SOF pattern at the beginning of each data stream. When the SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. Every completed byte is forwarded to the FIFO buffer. If an EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 138. Return values for bit-collision positions Collision in bit CollPos register value (Decimal) SOF 0 Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1 … … Most Significant Bit (MSB) of the LSByte 8 LSB of second byte 9 … … MSB of second byte 16 LSB of third byte 17 … … Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur after bit-collisions in the data bits.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.2.2.5 Communication errors The events which can set error flags are shown in Table 139. Table 139. Communication error table Cause Flag bit Received data did not start with the SOF pattern FramingErr CRC block is not equal to the expected value CRCErr Received data is shorter than the CRC block CRCErr The parity bit is not equal to the expected value (i.e.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.2.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.3 EEPROM commands 11.3.1 WriteE2 command 01h Table 142. WriteE2 command 01h Command Value Action FIFO Arguments and data WriteE2 01h get data from FIFO buffer and write it to the EEPROM Returned data start address LSB - start address MSB - data byte stream - The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.3.1.2 Timing diagram Figure 19 shows programming five bytes into the EEPROM. tprog,del NWR data write E2 addr LSB addr byte 0 MSB byte 1 byte 2 byte 3 Idle command byte 4 WriteE2 command active EEPROM programming tprog tprog tprog programming byte 0 programming byte 1, byte 2 and byte 3 programming byte 4 E2Ready TxIRq 001aak623 Fig 19.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.3.2 ReadE2 command 03h Table 143. ReadE2 command 03h Command Value Action Arguments Returned data ReadE2 03h start address LSB data bytes reads EEPROM data and stores it in the FIFO buffer start address MSB number of data bytes The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.4.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.4.2 CalcCRC command 12h Table 145.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.5 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. Table 147.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 15. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.6.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the MFRC530 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0).
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 13.2 Current consumption Table 154.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by a RC low-pass filter which causes a propagation delay on the reset signal. Table 157. RSTPD input pin characteristics Symbol Parameter Conditions ILI input leakage current Vth threshold voltage tPD Min Typ Max Unit 1.0 - A +1.0 positive-going threshold; CMOS = VDDD < 3.6 V 0.65VDDD - 0.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 13.3.3 Antenna driver output pin characteristics The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH-level can be configured using the CwConductance register’s GsCfgCW[5:0] bits, while their source conductance for driving the LOW-level is constant. The antenna driver default configuration output characteristics are specified in Table 160. Table 160.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution tLHLL ALE tSLRWL tRWHSH NCS tLLRWL tRWHRWL tRWLRWH tRWHRWL NWR NRD tAVLL D0 to D7 tWLQV tRLDV tLLAX A0 to A2 tWHDX tRHDZ D0 to D7 Multiplexed address bus tAVRWL A0 to A2 tWHAX A0 to A2 Separated address bus 001aaj638 Fig 20. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 162.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 163.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 13.4.4 SPI timing Table 164.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution recommended circuitry; see Section 9.8 on page 27. 14. EEPROM characteristics The EEPROM size is 32  16  8 = 4096 bit. Table 166. EEPROM characteristics Symbol Parameter Conditions Min Typ Max Unit Nendu(W_ER) write or erase endurance erase/write cycles 100000 - - Hz Tamb  55 C tret retention time 10 - - year ter erase time - - 2.9 ms ta(W) write access time - - 2.9 ms 15. Application information 15.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Refer to the following application notes for more detailed information about designing and tuning an antenna. • MICORE reader IC family; Directly Matched Antenna Design Ref. 1 • MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. 15.1.2.1 EMC low-pass filter The MIFARE system operates at a frequency of 13.56 MHz. This frequency is generated by a quartz oscillator to clock the MFRC530.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution The AC voltage divider of R1 + C3 and R2 has to be designed taking in to account the AC voltage limits on pin RX. Depending on the antenna coil design and the impedance, matching the voltage at the antenna coil will differ. Therefore the recommended way to design the receiver circuit is to use the given values for R1, R2, and C3; refer to Application note; MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution These measurements can be helpful during the design-in phase to optimize the receiver’s behavior, or for test purposes. 15.2.1 Measurements using the serial signal switch Using the serial signal switch on pin MFOUT, data is observed that is sent to the card or received from the card. Table 167 gives an overview of the different signals available. Table 167. Signal routed to pin MFOUT 15.2.1.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution (1) (2) (3) 10 μs per division 001aak626 (1) MFOUTSelect[2:0] = 3; serial data stream; 2 V per division. (2) MFOUTSelect[2:0] = 2; serial data stream; 2 V per division. (3) RFOut; 1 V per division. Fig 25. TX control signals 15.2.1.2 RX control Figure 26 shows an example of ISO/IEC 14443 A communication which represents the beginning of a card’s answer to a request signal.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution (1) (2) (3) 10 μs per division 001aak627 (1) RFOut; 1 V per division. (2) MFOUTSelect[2:0] = 4; Manchester with subcarrier; 2 V per division. (3) MFOUTSelect[2:0] = 5; Manchester; 2 V per division. Fig 26. RX control signals 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. Table 168.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 168. Analog test signal selection …continued Value Signal Name Description B VEvalR evaluation signal from the right half-bit C VTemp temperature voltage derived from band gap D reserved reserved for future use E reserved reserved for future use F reserved reserved for future use 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit. Finally, the digital test signal s_data shows the received data. This is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. RX reference VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid 50 μs per division 001aak628 Fig 27.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 16. Package outline SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 17. Abbreviations Table 170.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 19. Revision history Table 171. Revision history Document ID Release date Data sheet status Change notice Supersedes MFRC530 v. 3.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 22. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Quick reference data . . . . . . . . . . . . . . . . . . . . .
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MFRC530 NXP Semiconductors Standard MIFARE reader solution Table 70. TxControl register bit descriptions . . . . . . . . . .55 Table 71. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . .56 Table 72. CwConductance register bit descriptions . . . .56 Table 73. PreSet13 register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . . . . . . .56 Table 74. PreSet13 register bit descriptions . . . . . . . . . .56 Table 75.
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 137. Receive command 16h . . . . . . . . . . . . . . . . . .77 Table 138. Return values for bit-collision positions . . . . . .79 Table 139. Communication error table . . . . . . . . . . . . . . .80 Table 140. Transceive command 1Eh . . . . . . . . . . . . . . .80 Table 141. Meaning of ModemState . . . . . . . . . . . . . . . . .80 Table 142. WriteE2 command 01h . . . .
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 23. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. MFRC530 block diagram . . . . . . . . . . . . . . . . . . . .4 MFRC530 pin configuration . . . . . . . . . . . . . . . . . .5 Connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . .
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 24. Contents 1 2 3 3.1 4 5 6 7 8 8.1 9 9.1 9.1.1 9.1.2 9.1.3 9.1.3.1 9.1.3.2 9.1.3.3 9.1.4 9.1.4.1 9.1.4.2 9.2 9.2.1 9.2.2 9.2.2.1 9.2.2.2 9.2.2.3 9.2.3 9.2.3.1 9.2.3.2 9.3 9.3.1 9.3.1.1 9.3.2 9.3.3 9.3.4 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 9.4.3 9.4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . .
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 10 MFRC530 registers . . . . . . . . . . . . . . . . . . . . . 10.1 Register addressing modes . . . . . . . . . . . . . . 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Dedicated address bus . . . . . . . . . . . . . . . . . . 10.1.3 Multiplexed address bus . . . . . . . . . . . . . . . . . 10.2 Register bit behavior. . . . . . . . . . . . . . . . . . . . 10.3 Register overview . . . . . . . . . . . . . . . . . . . .
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MFRC530 NXP Semiconductors Standard MIFARE reader solution 11.3.2 ReadE2 command 03h . . . . . . . . . . . . . . . . . . 84 11.3.2.1 ReadE2 command error flags. . . . . . . . . . . . . 84 11.4 Diverse commands . . . . . . . . . . . . . . . . . . . . . 84 11.4.1 LoadConfig command 07h . . . . . . . . . . . . . . . 84 11.4.1.1 Register assignment . . . . . . . . . . . . . . . . . . . . 84 11.4.1.2 Relevant LoadConfig command error flags . . 85 11.4.2 CalcCRC command 12h . . . . . . . . . . . . . . . . .