Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsMFRC53101T/0FE,112

1. Introduction

This data sheet describes the functionality of the MFRC531 Integrated Circuit (IC). It

includes the functional and electrical specifications and from a system and hardware

viewpoint gives detailed information on how to design-in the device.

Remark: The MFRC531 supports all variants of the MIFARE Mini, MIFARE 1K,

MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus RF

identification protocols. To aid readability throughout this data sheet, the MIFARE Mini,

MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus

products and protocols have the generic name MIFARE.

2. General description

The MFRC531 is a highly integrated reader IC for contactless communication at

13.56 MHz. The MFRC531 reader IC provides:

• outstanding modulation and demodulation for passive contactless communication

• a wide range of methods and protocols

• a small, fully integrated package

• pin compatibility with the MFRC500, MFRC530 and SLRC400

All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication

standards are supported provided:

• additional components, such as the oscillator, power supply, coil etc. are correctly

applied.

• standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B

anticollision are correctly implemented

The MFRC531 supports contactless communication using MIFARE higher baud rates

(see Section 9.12 on page 38

). The receiver module provides a robust and efficient

demodulation/decoding circuitry implementation for compatible transponder signals (see

Section 9.10 on page 32

The digital module, manages the complete ISO/IEC 14443 standard framing and error

detection (parity and CRC). In addition, it supports the fast MIFARE security algorithm for

authenticating the MIFARE products (see Section 9.14 on page 40

The internal transmitter module (Section 9.9 on page 29

) can directly drive an antenna

designed for a proximity operating distance up to 100 mm without any additional active

circuitry.

MFRC531

Standard ISO/IEC 14443 A/B reader solution

Rev. 3.6 — 27 February 2014

056636

Product data sheet

COMPANY PUBLIC

Summary of content (117 pages)

PAGE 1
MFRC531 Standard ISO/IEC 14443 A/B reader solution Rev. 3.6 — 27 February 2014 056636 Product data sheet COMPANY PUBLIC 1. Introduction This data sheet describes the functionality of the MFRC531 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device.
PAGE 2
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility is supported (see Section 9.1.4 on page 9). 3. Features and benefits 3.
PAGE 3
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 4. Applications       Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems 5. Quick reference data Table 1. Quick reference data Symbol Parameter Min Typ Max Unit Tamb ambient temperature 40 - +150 C Tstg storage temperature 40 - +150 C VDDD digital supply voltage 0.5 5 6 V VDDA analog supply voltage 0.
PAGE 4
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 7.
PAGE 5
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 8. Pinning information OSCIN 1 32 OSCOUT IRQ 2 31 RSTPD MFIN 3 30 VMID MFOUT 4 29 RX TX1 5 28 AVSS TVDD 6 27 AUX 26 AVDD TX2 7 TVSS 8 NCS 9 MFRC531 25 DVDD 24 A2/SCK 23 A1 NWR/R/NW/nWrite 10 22 A0/nWait/MOSI NRD/NDS/nDStrb 11 21 ALE/AS/nAStrb/NSS DVSS 12 AD0/D0 13 20 D7/AD7 AD1/D1 14 19 D6/AD6 AD2/D2 15 18 D5/AD5 AD3/D3 16 17 D4/AD4 001aal219 Fig 2. MFRC531 pin configuration 8.
PAGE 6
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 3.
PAGE 7
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The MFRC531 supports direct interfacing to various 8-bit microprocessors. Alternatively, the MFRC531 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows the parallel interface signals supported by the MFRC531. Table 4.
PAGE 8
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. Table 5. Connection scheme for detecting the parallel interface type MFRC531 pins 9.1.3.
PAGE 9
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER MFRC531 non-multiplexed address NCS ADDRESS DECODER LOW A2 HIGH address bus (A0 to A2) A0 to A2 data bus (D0 to D7) A1 LOW A0 multiplexed address/data (AD0 to AD7) AD0 to AD7 D0 to D7 HIGH Address strobe (AS) ALE Data strobe (NDS) Read/Write (R/NW) MFRC531 NCS ALE Data strobe (NDS) NRD NRD Read/Write (R/NW) NWR NWR 001aal221 Fig 4.
PAGE 10
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 6. SPI compatibility MFRC531 pins SPI pins ALE NSS A2 SCK A1 LOW A0 MOSI NRD HIGH NWR HIGH NCS LOW D7 to D1 do not connect D0 MISO Figure 6 shows the microprocessor connection to the MFRC531 using SPI. MFRC531 LOW NCS SCK A2 LOW A1 MOSI A0 MISO D0 NSS ALE 001aal223 Fig 6.
PAGE 11
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 8. SPI read address Address (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) byte 0 1 address address address address address address reserved byte 1 to byte n reserved address address address address address address reserved byte n + 1 [1] 9.1.4.2 0 0 0 0 0 0 0 0 All reserved bits must be set to logic 0. SPI write data The structure shown in Table 9 must be used to write data using SPI.
PAGE 12
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.2 Memory organization of the EEPROM Table 11. EEPROM memory organization diagram Block MFRC531 Product data sheet COMPANY PUBLIC Byte address Access Memory content Refer to Position Address 0 0 00h to 0Fh R product information field Section 9.2.1 on page 13 1 1 10h to 1Fh R/W Section 9.2.2.
PAGE 13
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.2.1 Product information field (read only) Table 12.
PAGE 14
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Remark: The following points apply to initialization: • the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. • make sure that all PreSetxx registers are not changed. • make sure that all register bits that are reserved are set to logic 0. 9.2.2.
PAGE 15
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 15.
PAGE 16
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address 3 to 7 can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.4.1 on page 86). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. The byte assignment is shown in Table 16. Table 16.
PAGE 17
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Remark: It is possible to load data for other key formats into the EEPROM key storage location. However, it is not possible to validate card authentication with data which will cause the LoadKeyE2 command (see Section 11.6.1 on page 88) to fail. 9.2.3.2 Storage of keys in the EEPROM The MFRC531 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys.
PAGE 18
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 17. FIFO buffer access …continued Active command FIFO buffer p Write p Read Remark ReadE2 yes yes LoadKeyE2 yes - LoadKey yes - Authent1 yes - Authent2 - - LoadConfig yes - CalcCRC yes - the microprocessor has to prepare the arguments, afterwards only reading is allowed 9.3.
PAGE 19
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.3.4 FIFO buffer registers and flags Table 17 shows the related FIFO buffer flags in alphabetic order. Table 18.
PAGE 20
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 19.
PAGE 21
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.4.3 Configuration of pin IRQ The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be controlled using the following IRQPinConfig register bits. • bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq.
PAGE 22
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.5 Timer unit The timer derives its clock signal from the 13.56 MHz on-board chip clock. The microprocessor can use this timer to manage timing-relevant tasks.
PAGE 23
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.5.1 Timer unit implementation 9.5.1.1 Timer unit block diagram Figure 8 shows the block diagram of the timer module. TStartTxBegin TReloadValue[7:0] TxBegin Event TStartTxEnd PARALLEL IN TxEnd Event START COUNTER/ PARALLEL LOAD TAutoRestart TStartNow Q S COUNTER MODULE (x ≤ x − 1) TRunning Q R TStopNow STOP COUNTER RxEnd Event TStopRxEnd RxBegin Event TStopRxBegin TPreScaler[4:0] 13.
PAGE 24
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution The timer is started immediately by loading a value from the TimerReload register into the counter module.
PAGE 25
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event. If a given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt.
PAGE 26
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. The status of all pins during a hard power-down is shown in Table 23. Table 23.
PAGE 27
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state.
PAGE 28
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the description of each register (see Section 10.5 on page 48). Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable.
PAGE 29
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.8 Oscillator circuit MFRC531 OSCOUT OSCIN 13.56 MHz 15 pF 15 pF 001aal224 Fig 10. Quartz clock connection The clock applied to the MFRC531 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible.
PAGE 30
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 25. Pin TX2 configurations TxControl register configuration TX2RFEn FORCE100ASK TX2CW Envelope TX2 signal TX2Inv 0 X X X X LOW 1 0 0 0 0 13.56 MHz carrier frequency modulated 1 0 0 0 1 13.56 MHz carrier frequency 1 0 0 1 0 13.56 MHz carrier frequency modulated, 180 phase-shift relative to TX1 1 0 0 1 1 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 0 1 0 X 13.
PAGE 31
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.9.3.1 Source resistance table Table 26. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod MANT = Mantissa; EXP = Exponent. GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, RS(ref) MANTGsCfgMod () (decimal) GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () 0 0 0 - 24 1 8 0.
PAGE 32
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.9.3.2 Calculating the relative source resistance The reference source resistance RS(ref) can be calculated using Equation 6. 1 R S  ref  = ------------------------------------------------------------------------------EXP GsCfgCW 77  MANT GsCfgCW  ----- 40 (6) The reference source resistance (RS(ref)) during the modulation phase can be calculated using ModConductance register’s GsCfgMod[5:0]. 9.9.3.
PAGE 33
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitized and then passed to the digital circuitry. Various adjustments can be made to obtain optimum performance for all processing units. 9.10.
PAGE 34
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Automatic calibration can be set-up to execute at the end of each Transceive command if bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations except after the reset sequence. Automatic calibration can also be triggered by the software when bit ClkQCalib has a logic 0 to logic 1 transition.
PAGE 35
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.10.2.3 Correlation circuitry The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure of the amplitude of the expected signal in the received signal. This is done for both, the Q and I-channels. The correlator provides two outputs for each of the two input channels, resulting in a total of four output signals.
PAGE 36
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The Manchester signal and the Manchester signal with subcarrier can only be accessed on pin MFOUT at 106 kBd based on ISO/IEC 14443 A. 9.11.1 Serial signal switch block diagram Figure 13 shows the serial signal switches. Three different switches are implemented in the serial signal switch enabling the MFRC531 to be used in different configurations.
PAGE 37
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 28. DecoderSource[1:0] values See Table 93 on page 64 for additional information. Number DecoderSource Input signal to decoder [1:0] 0 00 constant 0 1 01 output of the analog part. This is the default configuration 2 10 direct connection to pin MFIN; expects an 847.
PAGE 38
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 31.
PAGE 39
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.13 ISO/IEC 14443 B communication scheme The international standard ISO/IEC 14443 covers two communication schemes; ISO/IEC 14443 A and ISO/IEC 14443 B. The MFRC531 reader IC fully supports both ISO/IEC 14443 variants. Table 33 describes the registers and flags covered by the ISO/IEC 14443 B communication protocol. Table 33.
PAGE 40
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.14 MIFARE authentication and Crypto1 The security algorithm used in the MIFARE products is called Crypto1. It is based on a proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards, knowledge of the key format is needed. The correct key must be available in the MFRC531 to enable successful card authentication and access to the card’s data stored in the EEPROM.
PAGE 41
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.14.2 Authentication procedure The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid authentication, the correct key has to be available in the key buffer of the MFRC531. This can be ensured as follows: 1. Load the internal key buffer by using the LoadKeyE2 (see Section 11.6.1 on page 88) or the LoadKey (see Section 11.6.2 on page 88) commands. 2. Start the Authent1 command (see Section 11.6.
PAGE 42
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 35. Multiplexed address bus: assembling the register address Multiplexed address bus type UsePage Register address Select Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0 Linear addressing 0 AD5 AD3 AD2 AD1 AD0 AD4 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers.
PAGE 43
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.3 Register overview Table 37.
PAGE 44
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 37.
PAGE 45
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.4 MFRC531 register flags overview Table 38.
PAGE 46
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 38.
PAGE 47
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 38.
PAGE 48
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. Table 39. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation Bit 10.5.1.2 7 6 5 4 Symbol UsePageSelect 0000 Access R/W R/W Table 40.
PAGE 49
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. Table 43. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation Bit 7 5 4 3 Symbol FIFOData[7:0] Access D Table 44. 10.5.1.4 6 2 1 0 FIFOData register bit descriptions Bit Symbol Description 7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer.
PAGE 50
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 46.
PAGE 51
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.1.6 SecondaryStatus register Various secondary status flags. Table 49. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation Bit 7 6 5 Symbol TRunning E2Ready CRCReady 00 RxLastBits[2:0] Access R R R R R Table 50.
PAGE 52
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.1.8 InterruptRq register Interrupt request flags. Table 53. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 Symbol SetIRq 0 TimerIRq TxIRq RxIRq Access W R/W D D D Table 54.
PAGE 53
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 48. 10.5.2.2 Control register Various control flags, for timer, power saving, etc. Table 55. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation Bit 7 5 4 Symbol 00 StandBy Access R/W D Table 56. 10.5.2.
PAGE 54
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 58. Bit Symbol Value Description 5 AccessErr 1 set when the access rights to the EEPROM are violated 0 set when an EEPROM related command starts 4 FIFOOvfl 1 set when the microprocessor or MFRC531 internal state machine (e.g.
PAGE 55
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.2.5 TimerValue register Value of the timer. Table 61. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation Bit 7 5 4 3 Symbol TimerValue[7:0] Access R Table 62. 10.5.2.6 6 2 1 0 TimerValue register bit descriptions Bit Symbol Description 7 to 0 TimerValue[7:0] this register shows the timer counter value CRCResultLSB register LSB of the CRC coprocessor register. Table 63.
PAGE 56
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 67. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation Bit 7 Symbol 0 RxAlign[2:0] 0 TxLastBits[2:0] Access R/W D R/W D Table 68.
PAGE 57
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 48. 10.5.3.2 TxControl register Controls the logical behavior of the antenna pin TX1 and TX2. Table 69. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation Bit 7 Symbol 0 Access R/W Table 70.
PAGE 58
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. Table 71. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 Symbol 00 GsCfgCW[5:0] Access R/W R/W Table 72.
PAGE 59
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 75. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation Bit 7 6 4 3 2 1 0 Symbol 00 CoderRate[2:0] TxCoding[2:0] Access R/W R/W R/W Table 76.
PAGE 60
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.3.8 TypeBFraming Defines the framing for ISO/IEC 14443 B communication. Table 80. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation Bit 7 Symbol NoTxSOF Access R/W Table 81.
PAGE 61
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 48. 10.5.4.2 RxControl1 register Controls receiver operation. Table 82.
PAGE 62
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.4.3 DecoderControl register Controls decoder operation. Table 84. Bit 7 6 Symbol 0 Access R/W Table 85.
PAGE 63
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. Table 88. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation Bit 7 5 4 3 2 1 Symbol MinLevel[3:0] CollLevel[3:0] Access R/W R/W Table 89. 10.5.4.6 6 0 RxThreshold register bit descriptions Bit Symbol Description 7 to 4 MinLevel[3:0] the minimum signal strength the decoder will accept.
PAGE 64
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. Table 92. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation Bit 7 6 Symbol RcvClkSelI RxAutoPD 0000 DecoderSource[1:0] Access R/W R/W R/W R/W Table 93.
PAGE 65
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 48. 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. Table 96. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation Bit 7 5 4 3 Symbol RxWait[7:0] Access R/W Table 97. 10.5.5.
PAGE 66
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 99. Bit Symbol Value Function 1 ParityOdd 1 odd parity is generated or expected[1] 0 even parity is generated or expected 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (MIFARE, ISO/IEC 14443 A) 0 no parity bit is inserted or expected (ISO/IEC 14443 B) 0 [1] 10.5.5.
PAGE 67
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.5.7 MFOUTSelect register Selects the internal signal applied to pin MFOUT. Table 105. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00000 MFOUTSelect[2:0] Access R/W R/W Table 106. MFOUTSelect register bit descriptions Bit Symbol Value Description 7 to 3 00000 - these values must not be changed 2 to 0 MFOUTSelect[2:0] [1] 10.5.5.
PAGE 68
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 48. 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. Table 108. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation Bit 7 6 5 4 3 2 Symbol 00 WaterLevel[5:0] Access R/W R/W 1 0 Table 109.
PAGE 69
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. Table 112. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin Access R/W R/W R/W R/W R/W Table 113.
PAGE 70
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. Table 116. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000000 IRQInv IRQPushPull Access R/W R/W R/W Table 117. IRQPinConfig register bit descriptions Bit Symbol Value Description 7 to 2 000000 - these values must not be changed 1 IRQInv 0 10.5.6.
PAGE 71
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 48. 10.5.8.2 Reserved register 39h Table 121. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Remark: This register is reserved for future use. 10.5.8.
PAGE 72
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.8.4 Reserved register 3Bh Table 124. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Table 125.
PAGE 73
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 10.5.8.7 Reserved registers 3Eh, 3Fh Table 128. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Remark: This register is reserved for future use. 11. MFRC531 command set MFRC531 operation is determined by an internal state machine capable of performing a command set.
PAGE 74
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 129. MFRC531 commands overview …continued Command Value Action FIFO communication Arguments and data sent Data received Transceive[1] 1Eh data stream transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11.2.3 on page 82.
PAGE 75
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.1.1 Basic states 11.1.2 StartUp command 3Fh Table 130. StartUp command 3Fh Command Value Action Arguments and data Returned data StartUp 3Fh runs the reset and initialization phase - - Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data.
PAGE 76
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.2 Commands for ISO/IEC 14443 A card communication The MFRC531 is a fully ISO/IEC 14443 A and ISO/IEC 14443 B compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE reader ICs. Section 11.2.1 to Section 11.2.5 describe the command set for ISO/IEC 14443 A card communication and related communication protocols. 11.2.1 Transmit command 1Ah Table 132.
PAGE 77
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bit; see Section 11.2.4 on page 82.
PAGE 78
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution TxLastBits[2:0] TxLastBits = 0 FIFOLength[6:0] 01h 00h FIFO empty TxData 7 0 7 0 7 check FIFO empty accept further data 001aak619 Fig 16. Timing for transmitting byte oriented frames As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The MFRC531 appends this data to the data stream transmitted using the RF interface.
PAGE 79
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Figure 17 also shows write access to the FIFOData register just before the FIFO buffer’s status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function.
PAGE 80
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution If an EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected.
PAGE 81
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 135.
PAGE 82
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.2.3 Transceive command 1Eh Table 137. Transceive command 1Eh Command Value Action Arguments and data Transceive 1Eh transmits data from FIFO buffer to the card data stream and then automatically activates the receiver Returned data data stream The Transceive command first executes the Transmit command (see Section 11.2.1 on page 76) and then starts the Receive command (see Section 11.2.2 on page 79).
PAGE 83
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.2.
PAGE 84
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.3 EEPROM commands 11.3.1 WriteE2 command 01h Table 139. WriteE2 command 01h Command Value Action FIFO Arguments and data WriteE2 01h get data from FIFO buffer and write it to the EEPROM Returned data start address LSB - start address MSB - data byte stream - The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address.
PAGE 85
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.3.1.2 Timing diagram Figure 19 shows programming five bytes into the EEPROM. tprog,del NWR data write E2 addr LSB addr byte 0 MSB byte 1 byte 2 byte 3 Idle command byte 4 WriteE2 command active EEPROM programming tprog tprog tprog programming byte 0 programming byte 1, byte 2 and byte 3 programming byte 4 E2Ready TxIRq 001aak623 Fig 19.
PAGE 86
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.3.2 ReadE2 command 03h Table 140. ReadE2 command 03h Command Value Action Arguments Returned data ReadE2 03h start address LSB data bytes reads EEPROM data and stores it in the FIFO buffer start address MSB number of data bytes The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned.
PAGE 87
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.4.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.4.2 CalcCRC command 12h Table 142.
PAGE 88
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.5 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. Table 144.
PAGE 89
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 16. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer.
PAGE 90
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.6.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the MFRC531 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0).
PAGE 91
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 13.2 Current consumption Table 151.
PAGE 92
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by a RC low-pass filter which causes a propagation delay on the reset signal. Table 154. RSTPD input pin characteristics Symbol Parameter Conditions ILI input leakage current Vth threshold voltage tPD Min Typ Max Unit 1.0 - A +1.0 positive-going threshold; CMOS = VDDD < 3.6 V 0.65VDDD - 0.
PAGE 93
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 157. Antenna driver output pin characteristics Symbol Parameter Conditions Min Typ VOH HIGH-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 4.97 - VDD(TVDD) = 5.0 V; IOL = 100 mA - 4.85 - V VOL LOW-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 30 - mV VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV output current transmitter; continuous wave; peak-to-peak - - 200 mA IO Max Unit V 13.
PAGE 94
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution tLHLL ALE tSLRWL tRWHSH NCS tLLRWL tRWHRWL tRWLRWH tRWHRWL NWR NRD tAVLL D0 to D7 tWLQV tRLDV tLLAX A0 to A2 tWHDX tRHDZ D0 to D7 Multiplexed address bus tAVRWL A0 to A2 tWHAX A0 to A2 Separated address bus 001aaj638 Fig 20. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care.
PAGE 95
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 159.
PAGE 96
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 160.
PAGE 97
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 13.4.4 SPI timing Table 161.
PAGE 98
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 14. EEPROM characteristics The EEPROM size is 32  16  8 = 4096 bit. Table 163. EEPROM characteristics Symbol Parameter Conditions Min Nendu(W_ER) write or erase endurance erase/write cycles Tamb  55 C Typ Max Unit 100.000 - - Hz tret retention time 10 - - year ter erase time - - 2.9 ms ta(W) write access time - - 2.9 ms 15. Application information 15.1 Typical application 15.1.
PAGE 99
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 15.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2n), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. Refer to the following application notes for more detailed information about designing and tuning an antenna. • MICORE reader IC family; Directly Matched Antenna Design Ref. 1 • MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. 15.1.2.
PAGE 100
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 15.1.2.3 Receiver circuit The internal receiver of the MFRC531 makes use of both subcarrier load modulation side-bands. No external filtering is required. It is recommended to use the internally generated VMID potential as the input potential for pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To provide a stable DC reference voltage, capacitor (C4) must be connected between VMID and ground.
PAGE 101
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 15.2 Test signals The MFRC531 allows different kinds of signal measurements. These measurements can be used to check the internally generated and received signals using the serial signal switch as described in Section 9.11 on page 35.
PAGE 102
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution (1) (2) (3) 10 μs per division 001aak626 (1) MFOUTSelect[2:0] = 001; serial data stream; 2 V per division. (2) MFOUTSelect[2:0] = 010; serial data stream; 2 V per division. (3) RFOut; 1 V per division. Fig 25. TX control signals 15.2.1.2 RX control Figure 26 shows an example of ISO/IEC 14443 A communication which represents the beginning of a card’s answer to a request signal.
PAGE 103
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution (1) (2) (3) 10 μs per division 001aak627 (1) RFOut; 1 V per division. (2) MFOUTSelect[2:0] = 011; Manchester with subcarrier; 2 V per division. (3) MFOUTSelect[2:0] = 100; Manchester; 2 V per division. Fig 26. RX control signals 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. Table 165.
PAGE 104
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 165. Analog test signal selection …continued Value Signal Name Description B VEvalR evaluation signal from the right half-bit C VTemp temperature voltage derived from band gap D reserved reserved for future use E reserved reserved for future use F reserved reserved for future use 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1.
PAGE 105
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit. Finally, the digital test signal s_data shows the received data. This is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. RX reference VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid 50 μs per division 001aak628 Fig 27.
PAGE 106
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 16. Package outline SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.
PAGE 107
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 17. Abbreviations Table 167.
PAGE 108
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 19. Revision history Table 168. Revision history Document ID Release date MFRC531 v. 3.6 20140227 Modifications: MFRC531_34 Modifications: Change notice Supersedes Product data sheet - MFRC531 v. 3.5 - MFRC531_34 - 056633 Section 2 “General description”: MFRC531 v. 3.
PAGE 109
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 110
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
PAGE 111
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 22. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Quick reference data . . . . . . . . . . . . . . . . .
PAGE 112
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 70. TxControl register bit descriptions . . . . . . . . . .57 Table 71. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . .58 Table 72. CwConductance register bit descriptions . . . .58 Table 73. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . .58 Table 74. ModConductance register bit descriptions . . . .58 Table 75.
PAGE 113
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution Table 136. Communication error table . . . . . . . . . . . . . . .81 Table 137. Transceive command 1Eh . . . . . . . . . . . . . . .82 Table 138. Meaning of ModemState . . . . . . . . . . . . . . . . .82 Table 139. WriteE2 command 01h . . . . . . . . . . . . . . . . . .84 Table 140. ReadE2 command 03h . . . . . . . . . . . . . . . . . .86 Table 141. LoadConfig command 07h . . . . . . . . . . . . . . .86 Table 142. CalcCRC command 12h .
PAGE 114
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 23. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. MFRC531 block diagram . . . . . . . . . . . . . . . . . . . .4 MFRC531 pin configuration . . . . . . . . . . . . . . . . . .5 Connection to microprocessor: separate read and write strobes . . . . . . . . . . . .
PAGE 115
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 24. Contents 1 2 3 3.1 4 5 6 7 8 8.1 9 9.1 9.1.1 9.1.2 9.1.3 9.1.3.1 9.1.3.2 9.1.3.3 9.1.4 9.1.4.1 9.1.4.2 9.2 9.2.1 9.2.2 9.2.2.1 9.2.2.2 9.2.2.3 9.2.3 9.2.3.1 9.2.3.2 9.3 9.3.1 9.3.1.1 9.3.2 9.3.3 9.3.4 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 9.4.3 9.4.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . .
PAGE 116
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 9.14.2 Authentication procedure . . . . . . . . . . . . . . . . 10 MFRC531 registers . . . . . . . . . . . . . . . . . . . . . 10.1 Register addressing modes . . . . . . . . . . . . . . 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Dedicated address bus . . . . . . . . . . . . . . . . . . 10.1.3 Multiplexed address bus . . . . . . . . . . . . . . . . . 10.2 Register bit behavior. . . . . . . . . . . . . .
PAGE 117
MFRC531 NXP Semiconductors Standard ISO/IEC 14443 A/B reader solution 11.3.1 WriteE2 command 01h . . . . . . . . . . . . . . . . . . 84 11.3.1.1 Programming process . . . . . . . . . . . . . . . . . . 84 11.3.1.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.1.3 WriteE2 command error flags . . . . . . . . . . . . . 85 11.3.2 ReadE2 command 03h . . . . . . . . . . . . . . . . . . 86 11.3.2.1 ReadE2 command error flags. . . . . . . . . . . . . 86 11.4 Diverse commands . . . . . . .