Datasheet

Table 49. Revision History (continued)
Rev. No. Date Substantial Changes
3 3/2011 Added sections that were inadvertently removed in previous revision
4 3/2011 Reworded I
IC
footnote in "Voltage and Current Operating Requirements" table.
Added paragraph to "Peripheral operating requirements and behaviors" section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
5 6/2011 • Changed supported part numbers per new part number scheme
• Changed DC injection current specs in "Voltage and current operating requirements"
table
• Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage
and current operating behaviors" table
• Split Low power stop mode current specs by temperature range in "Power
consumption operating behaviors" table
• Changed typical I
DD_VBAT
spec in "Power consumption operating behaviors" table
• Added LPTMR clock specs to "Device clock specifications" table
• Changed Minimum external reset pulse width in "General switching specifications"
table
• Changed PLL operating current in "MCG specifications" table
• Added footnote to PLL period jitter in "MCG specifications" table
• Changed Supply current in "Oscillator DC electrical specifications" table
• Changed Crystal startup time in "Oscillator frequency specifications" table
• Changed Operating voltage in "EzPort switching specifications" table
• Changed title of "FlexBus switching specifications" table and added Output valid and
hold specs
• Added "FlexBus full range switching specifications" table
• Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table
• Changed Gain spec in "16-bit ADC with PGA characteristics" table
• Added typical Input DC current to "16-bit ADC with PGA characteristics" table
• Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA
characteristics" table
• Changed Analog comparator initialization delay in "Comparator and 6-bit DAC
electrical specifications"
• Changed Code-to-code settling time, DAC output voltage range low, and Temperature
coefficient offset voltage in "12-bit DAC operating behaviors" table
• Changed Temperature drift and Load regulation in "VREF full-range operating
behaviors" table
• Changed DSPI_SCK cycle time specs in "DSPI timing" tables
• Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table
• Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high-
speed mode)" table
• Changed Reference oscillator current source base current spec and added Low-power
current adder footer in "TSI electrical specifications" table
6 01/2012 • Added AC electrical specifications.
• Replaced TBDs with silicon data throughout.
• In "Power mode transition operating behaviors" table, removed entry times.
• Updated "EMC radiated emissions operating behaviors" to remove SAE level and also
added data for 144LQFP.
• Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram".
• Added "ENOB vs. ADC_CLK for 16-bit differential and 16-bit single-ended modes"
figures.
• Updated I
DD_RUN
numbers in 'Power consumption operating behaviors' section.
• Clarified 'Diagram: Typical IDD_RUN operating behavior' section and updated 'Run
mode supply current vs. core frequency — all peripheral clocks disabled' figure.
• In 'Voltage reference electrical specifications' section, updated C
L
, V
tdrift
, and V
vdrift
values.
Table continues on the next page...
Revision History
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
66 Freescale Semiconductor, Inc.