Datasheet

S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 25. I
2
S timing — master mode
Table 45. I
2
S slave mode timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_BCLK cycle time (input) 8 x t
SYS
— ns
S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period
S13 I2S_FS input setup before I2S_BCLK 10 — ns
S14 I2S_FS input hold after I2S_BCLK 3 — ns
S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 20 ns
S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_BCLK 10 — ns
S18 I2S_RXD hold after I2S_BCLK 2 — ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
58 Freescale Semiconductor, Inc.