Datasheet

S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 26. I
2
S timing — slave modes
Table 46. I
2
S master mode timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 2 x t
SYS
ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_BCLK cycle time 5 x t
SYS
— ns
S4 I2S_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_BCLK to I2S_FS output valid — 15 ns
S6 I2S_BCLK to I2S_FS output invalid -4.3 — ns
S7 I2S_BCLK to I2S_TXD valid — 15 ns
S8 I2S_BCLK to I2S_TXD invalid -4.6 — ns
S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 23.9 — ns
S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns
Table 47. I
2
S slave mode timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_BCLK cycle time (input) 8 x t
SYS
— ns
S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period
S13 I2S_FS input setup before I2S_BCLK 10 — ns
S14 I2S_FS input hold after I2S_BCLK 3.5 — ns
S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 28.6 ns
S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_BCLK 10 — ns
S18 I2S_RXD hold after I2S_BCLK 2 — ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 59