Information

Section Number Title Page
10.2 Signal Multiplexing Integration....................................................................................................................................215
10.2.1 Port control and interrupt module features..................................................................................................216
10.2.2 Clock gating.................................................................................................................................................216
10.2.3 Signal multiplexing constraints....................................................................................................................216
10.3 Pinout............................................................................................................................................................................216
10.3.1 K10 Signal Multiplexing and Pin Assignments...........................................................................................217
10.3.2 K10 Pinouts..................................................................................................................................................223
10.4 Module Signal Description Tables................................................................................................................................225
10.4.1 Core Modules...............................................................................................................................................225
10.4.2 System Modules...........................................................................................................................................226
10.4.3 Clock Modules.............................................................................................................................................227
10.4.4 Memories and Memory Interfaces...............................................................................................................227
10.4.5 Analog..........................................................................................................................................................228
10.4.6 Communication Interfaces...........................................................................................................................230
10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................234
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................235
11.1.1 Overview......................................................................................................................................................235
11.1.2 Features........................................................................................................................................................235
11.1.3 Modes of operation......................................................................................................................................236
11.2 External signal description............................................................................................................................................237
11.3 Detailed signal descriptions..........................................................................................................................................237
11.4 Memory map and register definition.............................................................................................................................237
11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................244
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................246
11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................247
11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................247
11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................248
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
10 Freescale Semiconductor, Inc.