Information

3.5.3.2 SRAM Arrays
The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and
SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning
address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1]
This is illustrated in the following figure.
SRAM_U
0x2000_0000
SRAM size / 2
SRAM_L
0x1FFF_FFFF
SRAM size / 2
0x2000_0000 – SRAM_size/2
0x2000_0000 + SRAM_size/2 - 1
Figure 3-25. SRAM blocks memory map
For example, for a device containing 64 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_7FFF
3.5.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode.
In VLLS2 the 4 KB region of SRAM_U from 0x2000_0000 is powered.
Memories and Memory Interfaces
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
100 Freescale Semiconductor, Inc.