Information

(CH(n)FVAL[3:0] bits in FILTER0 register). The phase B input filter is enabled by
PHBFLTREN bit and this filter’s value is defined by CH1FVAL[3:0] bits (CH(n
+1)FVAL[3:0] bits in FILTER0 register).
Except for CH0FVAL[3:0] and CH1FVAL[3:0] bits, no channel logic is used in
quadrature decoder mode.
phase A input
system clock
phase B input
synchronizer
CH0FVAL[3:0]
PHAFLTREN
filtered phase A signal
PHAPOL PHBPOL
filtered phase B signal
PHBFLTREN
CH1FVAL[3:0]
synchronizer
Filter
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
Filter
Filter
FTM counter
direction
FTM counter
enable
up/down
CNTIN
MOD
TOFDIR
QUADIR
0
1
0
1
Figure 37-250. Quadrature Decoder Block Diagram
Note
It is important to notice that the FTM counter is clocked by the
phase A and B input signals when quadrature decoder mode is
selected. Therefore it is expected that the quadrature decoder be
used only with the FTM channels in input capture or output
compare modes.
The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects
the polarity of the phase B input.
The QUADMODE selects the encoding mode used in the quadrature decoder mode. If
QUADMODE = 1, then the count and direction encoding mode (see the following figure)
is enabled. In this mode, the phase B input value indicates the counting direction (FTM
counter increment or decrement), and the phase A input defines the counting rate (FTM
counter is updated when there is a rising edge at phase A input signal).
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1000 Freescale Semiconductor, Inc.