Information

When the FTM exits from reset:
• the FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] =
00b);
• the timer overflow interrupt is zero (Timer Overflow Interrupt);
• the channels interrupts are zero (Channel (n) Interrupt);
• the fault interrupt is zero (Fault Interrupt);
• the channels are in input capture mode (Input Capture Mode);
• the channels outputs are zero;
• the channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0:0) ().
The following figure shows the FTM behavior after the reset. At the reset (item 1), the
FTM counter is disabled (see the description of the CLKS field in the Status and Control
register), its value is updated to zero and the pins are not controlled by FTM ().
After the reset, the FTM should be configurated (item 2). It is necessary to define the
FTM counter mode, the FTM counting limits (MOD and CNTIN registers value), the
channels mode and CnV registers value according to the channels mode.
Thus, it is recommended to write any value to CNT register (item 3). This write updates
the FTM counter with the CNTIN register value and the channels output with its initial
value (except for channels in output compare mode) (Counter Reset).
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is
important to highlight that the pins are only controlled by FTM when CLKS[1:0] bits are
different from zero ().
(1) FTM reset
0x00160x00150x00140x00130x0011 . . .0x0010 0x00180x0017XXXX 0x0000 0x0012
FTM counter
CLKS[1:0]
channel (n) output
(4) write 1 to SC[CLKS]
(3) write any value
to CNT register
(2) FTM configuration
channel (n) pin is controlled by FTM
NOTES:
– CNTIN = 0x0010
– Channel (n) is in low-true combine mode with CNTIN < C(n)V < C(n+1)V < MOD
– C(n)V = 0x0015
00
XX
01
Figure 37-259. FTM Behavior After Reset When the Channel (n) Is in Combine Mode
Chapter 37 FlexTimer (FTM)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1009