Information

In VLLS1 no SRAM is retained. However, the 32-byte register file is available in

VLLS1.

3.5.3.4 SRAM accesses

The SRAM is split into two logical arrays that are 32-bits wide.

• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor

port.

• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the

backdoor port.

The backdoor port makes the SRAM accessible to the non-core bus masters (such as

DMA).

The following figure illustrates the SRAM accesses within the device.

Cortex-M4 core

Code bus

System bus

SRAM controller

Backdoor

SRAM_L

SRAM_U

Crossbar switch

non-core master

Frontdoor

MPU MPU

Figure 3-26. SRAM access diagram

The following simultaneous accesses can be made to different logical halves of the

SRAM:

• Core code and core system

• Core code and non-core master

• Core system and non-core master

NOTE

Two non-core masters cannot access SRAM simultaneously.

The required arbitration and serialization is provided by the

crossbar switch. The SRAM_{L,U} arbitration is controlled by

the SRAM controller based on the configuration bits in the

MCM module.

Chapter 3 Chip Configuration

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 101